A 1.8V/5GHz CMOS WLAN Low Noise Amplifier Integrated with Active BALUN Fernando Azevedo 1 , Luís Mendes 2 , Vitor Fialho 3 , João C. Vaz 4 , Fernando Fortes 5 and Maria J. Rosário 6 1,3,5 Instituto Superior de Engenharia de Lisboa, Lisboa, Portugal 2 Escola Superior de Tecnologia e Gestão, Instituto Politécnico de Leiria, Leiria, Portugal 4,6 Instituto Superior Técnico, Lisboa, Portugal 1,2,3,4,5,6 Instituto de Telecomunicações, Lisboa, Portugal 1 fazevedo@deetc.isel.ipl.pt , 5 ffortes@deetc.isel.ipl.pt and 6 mrosario@alfa.ist.utl.pt Abstract 1 — This paper presents the design and simulation of a 5GHz monolithic low-noise amplifier integrated with an active Balun. Intended to WLAN applications, the fully integrated circuit was implemented in a 0.18μm CMOS technology. The simulations, optimized to noise performance, gain and minimum differential phase and magnitude error, were performed with BSIM3 model. Circuit simulations present 23dB differential power gain at 5GHz, a phase and a transducer gain magnitude errors less than 1º and 0.2dB, respectively, in a 100MHz span around 5GHz, NF =3.6dB, 1dB CP = -22dBm, IIP3 = -8dBm, 50Ω input and output match, while drawing 8mA from a 1.8V power supply. Keywords — Balun, CMOS, Low Noise Amplifier (LNA), RF Integrated Circuit, Phase Converter, Wireless Communications. I. INTRODUCTION Wireless local-area networks (WLANs) have been deployed as office and home communications infrastructures worldwide. The diversification of the standards, such as IEEE 802.11 series demands the design of RF front-ends. Low power consumption is one of the most important design concerns in the application of those technologies. To maintain competitive hardware costs, CMOS has been used since it is the best solution for low cost and high integration level, allowing analog circuits to be mixed with digital ones. The development of high performance monolithic RF transceivers requires innovative RF circuit design to make the best of a good technology. In the receiver chain, the low noise amplifier (LNA) is one of the most critical blocks. The sensitivity is mainly determined by the LNA noise figure (NF) and gain. Furthermore, since it is the first gain stage, care must be taken to provide accurate input match, low NF, good linearity and a sufficient gain over a wide band of operation. A fully differential approach is usually preferred, due to its well-known properties. Although the differential approach must be preserved inside the chip, there are cases where the input signal is single-ended such as RF image filters and IF filters in a RF receiver. In these situations, a stage able to This research was funded by the project PTDC/EEA-ELC/64368/2006. convert single-ended into differential signals, known as Balun 1 , 2 is needed. This work reports the design and implementation [1] of a low power LNA, integrated with an innovative high- performance monolithic Balun on a 0.18μm CMOS process. The circuits presented here are aimed at IEEE 802.11a for WLAN applications. All the required circuits are integrated on the same die and are powered by 1.8V supply. The simulated results are shown, promising excellent experimental performance. Section II describes LNA and Balun topologies and the interconnected circuit design. Section III shows the simulated performance results focused at gain, phase/amplitude balance and noise figure. Finally, the last section draws conclusions and future work. II. DESCRIPTION OF THE CIRCUIT DESIGN A. Low Noise Amplifier topology The LNA must provide enough gain to reduce the impact of the following stages in the overall NF. As a first stage of receiver architecture, considerations like low NF and high gain must be taken into account during the LNA design. Besides that, linearity, input and output impedance match and stability (K f ) must also be considered. A classical noise matching technique was used. This technique, firstly reported in 1960 [2], was recently re-studied and reported in [3][4]. To allow a good compromise between high gain and low noise, a common source topology is preferable. A schematic of the proposed LNA is shown in Figure 1. It is a cascode common source topology, with a simple input and output matching network to enable wide band. Both input and output ports are matched to 50Ω. The predominant capacitive matching networks makes use of all parasitic elements to optimize input/output matching. B. Active Balun topology Several active Balun topologies have been proposed in the literature. The most cited and a strong candidate for use as active Balun is the differential topology shown in Figure 2. 1 BALUN - BALanced from UNbalanced signal converter.