IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN. VOL. zyxwvutsrq 11, NO. zyxwvutsrqp 1 I. NOVEMBER 1992 1459 Short Papers zyxw A Probabilistic Fault Model for “Analog” Faults in Digital CMOS Circuits Michele Favalli, P. Olivo, and Bruno Ricco Abstract-This paper presents a probabilistic approach to the detec- tion of analog faults (i.e., transistors stuck-on and bridgings) in CMOS circuits that depends on the conductances of faulty and fault-free net- works. It is shown that unrealistic fault coverages can be obtained by simply assigning constant values to the conductances of transistors and bridgings and by comparing the resultant conductances of faulty and fault-free conflicting networks. To solve this problem, in this paper all conductances are considered as random variables with normal distri- bution. Conductance distributions of complex conflicting networks can be easily evaluated and the detection probability of each fault is deter- mined. The expected coverage of analog faults is known at the end of a fault simulation. This result is shown to be more realistic than those obtained in a deterministic way. Fault coverages of analog faults ob- tained by means of a gate-level fault simulator are discussed for a com- plex FCMOS benchmark. I. INTRODUCTION CMOS digital integrated circuits present failure mechanisms that cannot be represented in terms of the classical line stuck-at fault model [1]-[3]. For instance, failures such as transistors stuck-on and bridgings may give rise to conductive paths between power supply and ground leading to intermediate zyxwvutsrqpo (analog) voltages at sig- nal nodes. The voltage value depends on the conductances of the networks connecting the signal lead to the power supply and to ground. The detection of such faults (hereafter collectively denoted as analog faults) as steady-state errors on primary outputs depends on the relative position of the faulty intermediate voltages with respect to the gate logic threshold. Hence, in order to determine whether or not an analog fault will be propagated as a logic error, the con- ductance conflicts originated by analog faults must be carefully taken into account in fault simulation, as is done in switch-level [4] and gate-level [5] fault simulators for FCMOS gates and macro- gates. Unfortunately, although correctly evaluating the conductances of complex networks, these simulators can produce unrealistic fault coverages. In these algorithms, in fact, conductance conflicts are solved by means of a threshold comparison between the conduc- tances of faulty and fault-free networks, and this approach can lead to large coverage differences depending on the considered value of conductances. As an example, Fig. 1 shows two different fault cov- erages for stuck-on faults for the FCMOS benchmark duke2 [6] obtained using the fault simulator described in [5]. Two different ratios between the conductance of a faulty device and that of the fault-free case are considered: 1 .O (curve zyxwvutsrqp a) and 1.05 (curve b). In addition, in actual CMOS circuits the conductances of ON transis- tors with the same nominal size generally differ from each other because of process random irregularities. The same consideration Manuscript received July 30, 1990; revised October 28. 1991; This pa- The authors are with D.E.I.S., University of Bologna, 40136 Bologna, IEEE Log Number 9200824. per was recommended by Associate Editor F. Brglez. Italy. 100 , I , I l l zyxw 80 I 01 , , 1 0 zyxwvutsr 25 50 zyxwvu 75 100 125 zyx TEST NO Fig. I. Stuck-ons coverages for the FCMOS benchmark duke2 assuming two different ratios between the conductance of a faulty transistor and that of the fault-free transistor. The ratio is 1 .O (curve a) and I .05 (curve b). The same pseudorandom sequence was used for the two cases. is even stronger for faulty devices and bridging paths, since the actual faulty conductances depend on the physical failure mecha- nisms. To take into account this problem, in this paper we present a different approach to the fault simulation of analog faults, treating them in a probabilistic way. In particular, we consider fault-free and faulty conductances as random variables, assuming normal dis- tributions 171. Starting from the conductance distributions of fault-free and faulty devices and of extra conductive paths (when considering bridging faults), the conductance distributions of conflicting net- works can be easily evaluated. Then, for a given test vector, the probability to detect each analog fault can be determined. For a given test sequence, the detection probability of each analog fault coincides with the maximum detection probability provided by all the test vectors. As a consequence, the expected fault coverages for analog faults can be easily determined as a final result of a fault simulation. This method is general and can be applied to gate- and switch- level fault simulators able to evaluate correctly the conductances of complex networks. As an application, we present results ob- tained on duke2 by means of a gate-level simulator able to treat complex FCMOS gates. 11. PROBABILISTIC EVALUATION OF CONDUCTANCES The conductances g of normally ON transistors, faulty transis- tors, and bridging paths are considered as independent random variables with a normal distribution N( p8, zyxwv U:) characterized by a mean value p,? and a variance U,. For the purpose of calculation, the resistances are also approximated by a normal distribution N( p,, U:) where the mean value p,. and the variance ur are given by 1 P, PS pc p, = - and U, = - U, 0278-0070/92$03.00 zyxwvuts 0 1992 IEEE