Statistical Bellman-Ford Algorithm With An Application to Retiming Mongkol Ekpanyapong Thaisiri Waterwai † Sung Kyu Lim School of Electrical and Computer Engineering † Dept. of Industrial Engineering and Operations Research Georgia Institute of Technology University of California, Berkeley {pop, limsk}@ece.gatech.edu thaisiri@uclink.berkeley.edu Abstract— Process variations in digital circuits make sequential circuit timing validation an extremely challenging task. In this paper, a Statistical Bellman-Ford (SBF) algorithm is proposed to compute the longest path length distribution for directed graphs with cycles. Our SBF algorithm efficiently computes the statistical longest path length distribution if there exist no positive cycles or detects one if the circuit is likely to have a positive cycle. An important application of SBF is Statistical Retiming- based Timing Analysis (SRTA), where SBF is used to check for the feasibility of a given target clock period distribution for retiming. Our gate and wire delay distribution model considers several high-impact intra-die process parameters and accurately captures the spatial and reconvergent path correlations. The Monte Carlo simulation is used to validate the accuracy of our SBF algorithm. To the best of our knowledge, this is the first paper that propose the statistic version of the longest path algorithm for sequential circuits. I. I NTRODUCTION Process variations in digital circuits make circuit timing validation an extremely challenging task. Variations on several high-impact intra-die process parameters such as effective gate length, wire width, and so forth, can easily invalidate the timing predictions made before the fabrication [1]. Therefore, statistical timing analysis tools that model gate and wire delay as probability distribution function became increasingly popular to tackle the timing validation under process variations [2], [3], [4]. However, most of the existing works focus on combinational circuits or sub-circuits (after FF removal) and fail to address sequential circuit timing validation directly. Par- titioning circuit into sub-circuits and solving the problem on a sub-circuit by sub-circuit basis lead to a sub-optimal solution. By considering the sequential circuit, timing analysis can be done by using longest path algorithms that can handle graphs with negative cycles such as the Bellman-Ford algorithm. There are many CAD algorithms that adopt the Bellman- Ford algorithm including scheduling[5], clock scheduling[6], verification[7], and retiming [8]. A recent work on static timing analysis for sequential circuits [8] allows the users to model FFs and use them to predict the timing information after retiming. This work achieves a significant performance improvement by exploiting retiming-aware timing slack. Our goal in this paper is to develop the Statistical Bellman-Ford (SBF) algorithm. In addition, we show an application of SBF on global placement using retiming [8]. In this paper, we first develop a Statistical Bellman-Ford (SBF) algorithm to compute the longest path length distribu- tion for directed graphs with negative cycles. We first prove that a statistical extension of the original Bellman-Ford algo- rithm correctly computes the longest path length distribution for the true distribution, but it requires infinite amount of time for the continuous distribution. Next, we show that two straightforward extensions of the Bellman-Ford algorithm for statistical analysis can not guarantee the correctness of the results. Lastly, we propose our SBF algorithm that closely approximates and efficiently computes the statistical longest path length distribution if there exists no positive cycles or detects one if the circuit is likely to have a positive cycle. Our SBF algorithm is integrated into SRTA, where SBF checks for the feasibility of a target clock period distribution for retiming. We show that the final critical path delay distribution after retiming is the statistical maximum among all primary outputs and all feedback vertices. The Monte Carlo simulation is used to validate the accuracy of our SRTA algorithm. The remainder of the paper is organized as follows. Section II presents our statistical Bellman-Ford algorithm. Section III presents our statistical retiming-based algorithm and its application in retiming. We present the experimental results in Section IV and conclude in Section V. II. STATISTICAL BELLMAN-FORD ALGORITHM We first provide the analysis of statistical longest path algo- rithm for the sequential circuit including its properties. Next, we show that the simple modified Bellman-Ford algorithms can not compute the statistical longest path correctly. Finally, we propose a modified version of the Bellman-Ford algorithm that closely approximates the statistical longest path length distribution for the sequential circuit. A. Statistical Longest Path Analysis We first introduce a stochastic version of the Bellman- Ford algorithm that correctly solves the stochastic longest path problem for true distribution. Before we do so, we first introduce some quantities in the probability theory that are required to develop algorithms. For more precise definitions of the quantities, see [9], [10]. Let Ω be the set of outcomes of a fabrication process. A subset of Ω is called an event. Let P be a function that assigns a probability to each event. A random