Voltage Buffer Compensation using Flipped Voltage Follower in a Two-Stage CMOS Op-amp Sri Harsh Pakala, Mahender Manda, Punith R. Surkanti, Annajirao Garimella and Paul M. Furth VLSI Laboratory, Klipsch School of Electrical and Computer Engineering New Mexico State University, Las Cruces, NM 88003, USA. Email: sriharsh@nmsu.edu Abstract—In Miller and current buffer compensation tech- niques, the compensation capacitor often loads the output node. If a voltage buffer is used in feedback, the compensation capacitor obviates the loading on the output node. In this paper, we introduce an implementation of a voltage buffer compensation using a Flipped Voltage Follower (FVF) for stabilizing a two-stage CMOS op-amp. The op-amps are implemented in a 180-nm CMOS process with a power supply of 1.8V while operating with a quiescent current of 110µA. Results indicate that the proposed voltage buffer compensation using FVF improves the Unity Gain Frequency from 5.5MHz to 12.2MHz compared to Miller compensation. Also, the proposed technique enhances the transient response while lowering the compensation capacitance by 47% and 17.7% compared to Miller and common-drain compensation topologies. Utilization of FVF or its variants as a voltage buffer in a feedback compensation network has wide potential applications in the analog design space. Index Terms—Flipped voltage follower, frequency compen- sation, CMOS op-amps, voltage buffers, current buffers. I. INTRODUCTION Miller [1], cascode [2], nested Miller (NM) and reverse- nested Miller (RNM) compensation schemes are the most widely used techniques to stabilize multi-stage amplifiers [3]- [21]. These compensation techniques are generally robust and offer advantages such as: (i) pole splitting, (ii) Left-Half-Plane (LHP) zero creation and its accurate placement through a nulling resistor and (iii), in the case of cascode compensation, eliminating the feed-forward path due to the presence of a current buffer, which is usually implemented with a common- gate transistor [5]-[14]. These techniques typically exhibit one inherent disadvantage, in which the compensation capacitor loads the output node. For example, Miller compensation between input node X and output node Y of the gain stage shown in Fig. 1(a) loads the output with the compensation capacitor, as node X is approximately an AC ground compared to node Y. For stabilizing an op-amp designed specifically for high-speed applications, it is immensely important to reduce the loading effect on the output in order to achieve a fast and stable transient response. Buffers introduced in the compensation path do not affect the gain, but assist in reducing the loading effect on the output node. These buffers in compensation path eliminate the feed-forward path and generate LHP zeros. A current buffer (CB) when introduced in feedback compensation network as shown in Fig. 1(b) can be very effective due to its low input impedance, represented by r i_CB . While the utilization of the low-impedance node as a compen- Fig. 1. Figure illustrating the loading of compensating capacitance on output node Y in case of (a) Miller compensation with nulling resistor and (b) current buffer. In case of (c) voltage buffer, compensating capacitance doesn’t load the output node Y. -sating node in compensation schemes using CBs helps in reducing the size of compensating capacitor C CB that is required to ensure a stable system, the output node Y is still loaded by C CB . Fig. 1(c) shows a voltage buffer (VB) introduced in the feedback compensation path between node Y and X in series with capacitance C VB . The elimination of a direct connection of C VB to the output improves the transient response. The low impedance node at the output of the VB provides an additional advantage of establishing effective feedback [11], [22]-[23]. Thus a VB with very low output impedance r 0 _ VB is preferred. Practical VBs can be implemented using a common-drain (CD) transistor. This paper introduces a VB compensation using a variant of the flipped voltage follower (FVF). In many applications, FVFs exhibit enhanced performance compared to a regular CD topology because of their very low output impedance [24]. In Section II, VB circuit topologies are analyzed and compared. Section III outlines the implementation details of the proposed compensation technique. Section IV presents the simulation results of Miller, CD and the proposed FVF compensation schemes. Section V illustrates the benefits of the FVF configuration over Miller and CD compensation schemes. Conclusions are presented in Section VI. II. VOLTAGE BUFFERS This section describes the implementation of different types of VBs suitable for compensation networks. A. Common-Drain Topology: The PMOS version of CD amplifier is shown in Fig. 2(a). Input V IN is applied to the PMOS CD transistor M CD , while the