Bias-Line Compensation in Multi-Stage Amplifers Punith R. Surkanti and Paul M. Furth Klipsch School of Electrical and Computer Engineering, New Mexico State University, Las Cruces, NM 88003, USA Email: punith@nmsu.edu, pfurth@nmsu.edu Abstact-In this paper, a novel bias-line compensation (BLC) using inverting current bufer for multi-stage amplifers is pro posed. This technique uses a compensation capacitor connected between the output node and low-impedance bias line, which helps in increasing the bandwidth and improving PSRR. The proposed technique is implemented in a widely-adopted low voltage, high-gain and wide-swing pseudo-class AB amplifer [1]. The amplifer is conventionally compensated with reverse-nested Miller compensation. The results show that bias-line compensa tion improves the bandwidth by 50% and PSRR by 5dB with ±1.25V power supplies. The amplifer with bias-line compensa tion is stable for a capacitive load in the range of IpF to 200pF. The chip was fabricated in a 0.5Jm 2P3M process. Measurement results validate the efectiveness of the proposed method. Fig. I. Schematic of three-stage pseudo-class AB amplifer, based on [1]. I. INTRODUCTION As technology advances, parameters such as transistor size and supply voltage are decreasing. This results in a reduction of gain for a single-stage amplifer. The best method to achieve high gain is by cascading amplifers, where the total gain is the product of the gains of each stage. The output swing is maximized for common-source output stages, resulting in rail to-rail output swing [2]. As the number of stages increases, the stability of the overall amplifer becomes more difcult to guarantee. Widely-used compensation techniques for multi stage amplifer are nested Miller compensation (NMC) [3], [4] and reverse NMC (RNMC) [ 1], [4]-[6]. Several variants of these techniques have also been proposed [4], [5], [7]. A Miller compensation capacitor in series with a voltage or current buffer, for example, helps in increasing stability. Instead of creating an extra branch in the circuit for the bufers, designers take advantage of one or more embedded bufers inside multi-stage amplifers. For example, cacode transistors are used as current bufers, as initially proposed in [8] [ 10], in which the compensation capacitor goes to the source of a cascode tansistor. Inverting current bufers generated from current mirrors are used in [7], [ 1 1]-[ 14]. This type of compensation simultaneously decreases the compensation capacitor value and increases amplifer bandwidth. The amplifer in Fig. 1 is an NMOS version of the pseudo class A amplifer in [ 1], a high gain multi-stage amplifer with a simple biasing circuit, low transistor-count and wide output-swing. The amplifer operates with low supply voltages and bias currents. It is found in a wide range of applica tions [7], [ 15], [ 16]. In this paper, we propose a novel bias-line compensation (BLC) technique that improves stability, bandwidth and PSRR. Section II introduces the pseudo-class A amplifer in which Fig. 2. Architecture of three·stage pseudo·c1ass AB amplifer of Fig. 1. we implemented the proposed compensation. Section III ex plains the proposed bias-line compensation and includes the small-signal model and pole-zero analysis. Section V summa rizes hadware and simulation results, comparing RNMC with and without the proposed BLC technique. The conclusion is discussed in Section ?? II. THREE-STAGE PSEUDO-CLASS AB AMPLIFI ER The schematic of three-stage pseudo-class AB amplifer is shown in Fig. 1. The frst stage is a diferential amplifer and the next two stages ae common-source amplifers. The PMOS transistor MpF, which is an inverting common-source amplifer, creates a feed-forward path from the intermediate node to the output node. RNMC with nulling resistor is used to stabilize the amplifer for a wide range of capacitive loads. Miller compensation without nulling resistor has the dis advantage of introducing a right half-plane (RHP) zero. Other compensation schemes, such as cascode compensation [9] and split-length tansistor compensation [2], introduce lef half plane (LHP) zeros. However, since there ae no cascoding 978-1-61284-857-0/11/$26.00 <2011 IEEE