0741-3106 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/LED.2018.2840507, IEEE Electron Device Letters > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 1 Abstract— Ruthenium (Ru) and cobalt (Co) are new candidates for the replacement of physical vapor deposition (PVD) tantalum (Ta) in liner materials because Ru and Co have excellent Cu-filling properties when deposited using chemical vapor deposition (CVD). Under accelerated current stressing conditions, Cu interconnects on a TaN/Co barrier showed an abrupt increase in resistance. The Cu resistance on a TaN/Ru barrier increased gradually and saturated with low deviation because voids generated randomly, and the Cu that remained on the Ru in the voids acted as shunt layers, preventing a sudden increase in resistance. Cu evolution tests on a Ru liner indicated that Cu had a strong bond with CVD Ru liner, even at high temperatures. These results suggest that Cu deposited on a TaN/Ru barrier can endure electromigration (EM) failure. Index Terms—Copper, ruthenium, cobalt, electromigration (EM), interconnects, CVD liner I. INTRODUCTION N RECENT logic interconnection structures, Cu interconnects are typically fabricated using a dual-Damascene process. The low-k inter-layer dielectric (ILD) layer is etched and deposited as a TaN/Ta double layer by physical vapor deposition (PVD) to form a Cu diffusion barrier. PVD seed Cu is then deposited on the TaN/Ta barrier to provide conductivity required by electroplating Cu layer. Then, the Cu interconnects are completed by electroplating the damascene structure with Cu [1, 2]. In the process of integrating the Cu interconnects, many PVD processes place small pitches in the damascene structures, resulting in overhangs that cause voids in the Cu interconnects and can become a serious problem. Therefore, much research has been conducted to create new materials that can overcome the problems of high resistance and low reliability caused by the generation of voids. Chemical Manuscript received May 4, 2018; revised , ; accepted , . Date of publication , ; date of current version , . The review of this letter was arranged by . This work is supported by the Samsung Electronics’ University R&D program (0417-20170071). [The study of high reliability Cu interconnects for next generation beyond 10 nm logic devices] Kyung-Tae Jang, So-Yeon Lee, Se- Kwon Na, Sol-Kyu Lee and Young-Chang Joo are with the Department of Materials Science and Engineering, Seoul National University, 1 Gwanak-ro, Gwanak-gu, Seoul 08826 Korea (e-mail: ycjoo@snu.ac.kr). Jong-Min Baek, Woo-Kyung You, Ok-Hee Park, Rak-Hwan Kim and Hyeok-Sang Oh are with the Process Development Team 2, Samsung Electronics Co., Ltd, 1 Samsungjeonja-ro, Hwaseong-si, Gyeonggi-do 18448 Korea. vapor deposition (CVD) has attracted attention in Cu interconnects because it can reduce overhangs in filling gaps of narrow areas. Recently, Co and Ru materials have also attracted attention as promising candidates for Cu liner because they have good adhesion to Cu and they are stable in thermodynamic [3]. Furthermore, they can be deposited using CVD to obtain a high step-coverage deposition with low resistance and low solubility of Cu [4, 5]. For these reasons, CVD Co and Ru materials have recently been selected as liners for adhesion and for Cu filling in Cu interconnects. However, despite these advantages, the electromigration (EM) reliability of Cu interconnects on Co and Ru materials has only been reported in terms of the device's failure lifetime [3, 6-9]. Because EM is a phenomenon in which metal atoms move along with the flow of electrons and cause voids or extrusions in the flux divergence sites, the high current densities and temperatures associated with the miniaturization of devices significantly accelerate the EM, resulting in open circuit failure with smaller pitches than before. Because highly integrated devices beyond 10nm are expected to have a difficulty filling gaps of Cu interconnects due to extreme pitch reduction, CVD liners have been adopted. In, this study, we will discuss the EM failure mechanism of Cu interconnects on CVD liners. To identify the differences in the EM behavior of Cu interconnects applied to a CVD liner, the morphological evolutions of Cu thin films at increasing temperatures will be discussed. II. DEVICE FABRICATION The samples used for testing EM reliability were prepared with Cu interconnects in the form of 48 nm pitch lines of 10 nm class logic devices with a dual-Damascene structure, and test lines were fabricated over 100 μm. Low-k (k ~ 2.7) material was used as the IMD layer. The Cu interconnect was made of Co or Ru material deposited by CVD on a PVD TaN. The Co or Ru served as the liner material in the dual-damascene structure, and the device fabrication was completed with using PVD to add seed Cu, followed by electroplating Cu as the interconnect material. When applied to Co liner, Cu interconnects adopted Co capping after CMP process. However, Cu interconnects with Ru liner did not adopt Co capping because the integration for Ru liner was not matured at the development of the devices. EM experiments were performed on an upstream path with Cu interconnects. The test equipment for EM was a Qualitau Inc. MIRA EM tester. The temperature range under accelerated Electromigration Characteristics and Morphological Evolution of Cu Interconnects on CVD Co and Ru Liners for 10 nm Class VLSI Technology Kyung-Tae Jang, So-Yeon Lee, Se- Kwon Na, Sol-Kyu Lee, Jong-Min Baek, Woo-Kyung You, Ok-Hee Park, Rak- Hwan Kim, Hyeok-Sang Oh and Young-Chang Joo * I