ISSN (Print) : 2320 – 3765 ISSN (Online): 2278 – 8875 International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering (An ISO 3297: 2007 Certified Organization) Vol. 4, Issue 3, March 2015 Copyright to IJAREEIE 10.15662/ijareeie.2015.0403026 1348 Design of Carry Select Adder for FIR Filter Prof. V. G. Raut 1 , Ashwini Lokhande 2 Assistant Professor, Dept. of E&TC, Sinhgad College of Engineering, Vadgaon(BK), Pune, India 1 PG Student [VLSI & Embedded Systems], Sinhgad College of Engineering, Vadgaon(BK), Pune, India 2 ABSTRACT: A fast and power efficient adder is always needed in electronic industry and is one of the vast area of research in VLSI system design. In this paper, design of two different Carry Select Adder (CSLA) are presented, one by using multiple pairs of RCA and another by using D-latch logic. Designing Carry Select Adder with RCA slightly increases the delay. To overcome this problem, CSLA is improved by replacing one of the RCA by D-latch. The performance of this CSLA is evaluated by implementing an FIR Filter by using CSLA in the adder part of filter. This work focuses on the performance of CSLA in terms of delay and power. KEYWORDS: CSLA, RCA, D-Latch, FIR Filter, Low power and high speed. I.INTRODUCTION Adders are very important in variety of digital system. Many fast adder exits, but adding fast with low delay and power is still challenging. In many computers and other kind of processor adders are used not only in the arithmetic logic units, but also in other part of processor, where they are used to calculate addresses, table indices, and similar operations. On the basis of requirements such as area, delay and power consumption there are some complex adders such as Ripple Carry Adder, Carry look-Ahead Adder and Carry Select Adder. Ripple Carry Adder (RCA) shows the compact design but their computation time is longer. Applications that has time as a critical factor make use of Carry Look-Ahead Adder (CLA) to derive fast results but it leads to increase in area. But the carry select adder provides a compromise between the small areas but longer delay of RCA and large area with small delay of Carry Look Ahead adder. The CSLA is used in many computational systems to improve the problem of carry propagation delay by independently generating multiple carries and then select a carry to generate the sum. However, the CSLA is not area efficient because it uses multiple pairs of RCA to generate partial sum and carry by considering carry in 0 and carry in 1, then the final sum and carry are selected by the multiplexers (mux). Now a day an electronics industry focuses on high speed application with low power consumption. Battery life in portable electronic device is limited. Low power design leads to increase in battery life. If delay is less, application will work fast and ultimately power consumption is low. So, there is a need to work on delay. II. LITERATURE SURVEY Akhilash Tyagi introduced a scheme to generate carry bits with block carry in 1 from the carries of a block with block with block carry in 0.This scheme is then applied to carry select and parallel-prefix adders to derive a more area- efficient implementation for both the cases [1]. Chang and Hsiao proposed that instead of using dual RCA a CSLA scheme using an add one circuit to replace one RCA, here it reduces fewer transistors [2]. Yajuan He et al proposed an area efficient square root carry select adder scheme based on a new first zero detection logic. The proposed CSL witnesses a notable power-delay and area-delay performance improvement by virtue of proper exploitation of logic structure and circuit technique [3]. Padma Devi et al proposed modified CSLA designed in different stages which reduces the area [4]. Ramkumar and Harish propose BEC technique which is a simple and efficient gate level modification to significantly reduce the area and power of square root CSLA [5]. Sajesh Kumar U, Mohamed Salih K. and Sajith K propose carry select adder without using multiplexer which reduce area and power consumption. The Kogge Stone parallel approach will give option to generate fast carry for intermediate stages [6].