Throughput Aware Mapping for Network on Chip Design of H.264 Decoder Vu-Duc Ngo, Huy-Nam Nguyen 1 , Younghwan Bae 2 , Hanjin Cho 2 , and Hae-Wook Choi 1 1 System VLSI Lab, SITI Research Center, School of Engineering Information and Communications University (ICU) Yusong P.O. Box 77, Taejon 305-714, Korea 2 Basic Research Laboratory, ETRI, Daejeon, Korea {duc75, huynam, hwchoi}@icu.ac.kr, {yhbae, hjcho}@etri.re.kr Abstract. Network-on-Chip (NoC) has been proposed as a new method- ology for addressing the design challenges of future massly integrated sys- tem in nanoscale. In this paper, we present the queuing theory based model for router to evaluate the performance of NoC in terms of drop probability, throughput and energy consumption. Then we apply the lin- ear programming to optimize the allocation of the heterogeneously func- tional blocks (IPs) onto the given heterogeneous NoC architecture so as to obtain the maximum throughput as well as to optimize the energy dissipation of whole system. Finally, the three differently heterogenous Tree-based network topologies are proposed as the NoC architectures for the study case of H.264 Decoder. This paper also evaluates the proposed topologies by comparing them to other conventional topologies such as 2-D Mesh and Fat-Tree with respects to throughput, power consumption and size. We use the power modelling tool, known as Orion model to cal- culate the static powers, areas, and dynamic powers of three topologies. The experiment results show that our Tree-based topologies offer similar throughputs as Fat-Tree does and much higher throughputs compared to 2-D Mesh while use less chip areas and energy consumptions. 1 Introduction According to [1], the Ultra Large Scale Integration (ULSI) will be the future of chip design. The idea of using NoC as the new design methodology to massly integrate the IPs such as processors, DSPs, as well as memory array was pro- posed in [2,3]. The packet switching core and the communication protocols are used to replace the complex system of wires or the main factors that lead to the propagation delay exceeding the system’s clock period and non-scalable global wire. However, the NoC design methodology poses complex design challenges to meet the requirement of throughput, area, reliability, and power consumption. The tile-based NoC with various applications and regular topologies such as 2D Mesh, Fat-Tree, and Torus were proposed in [4, 5, 14]. The authors in [6, 7, 8] had different approaches for the NoC design. They proposed the algorithms G. Min et al. (Eds.): ISPA 2006 Ws, LNCS 4331, pp. 791–802, 2006. c  Springer-Verlag Berlin Heidelberg 2006