Circuits Syst Signal Process DOI 10.1007/s00034-016-0485-2 Phase Detector with Minimal Blind Zone and Reset Time for GSamples/s DLLs Mohammad Gholami 1 Received: 2 April 2016 / Revised: 22 December 2016 / Accepted: 23 December 2016 © Springer Science+Business Media New York 2017 Abstract A new phase detector for high-speed applications is proposed in this paper. Due to their long reset path, conventional phase detectors can work in lower frequen- cies. However, the proposed phase detector has lower reset path delay in which makes it suitable for high-speed phase locked loops (PLL) and delay locked loops (DLL). Moreover, this new phase detector uses a few transistors. The proposed circuit is designed based on TSMC 0.13 μm CMOS Technology. Simulations show lower reset path delay, blind zone and power consumption for proposed architecture in compari- son with pervious related works. In addition, the circuit is able to detect phase offsets in about 80 ps and to work properly in frequencies near 3 GHz. Its blind zone is about 120 ps, while its reset path delay is about 80 ps. Furthermore, the power consumption of the proposed circuit at 128 MHz is found to be about 134 μW. Keywords Phase detector · High speed · Reset time · Blind zone · Low Power 1 Introduction Increasing advances in CMOS technology have led to boosting demands for high- speed and high-performance circuits. Delay locked loops (DLLs) and phased locked loops (PLLs) are widely used in clock synchronization circuits, frequency synthesizers [5], digital transceivers, DRAMs [13], SRAMs and clock and data recovery circuits. One of the main building blocks in both DLLs and PLLs is phase detector [6]. This fact has led to increasingly significant role of phase detector in high-speed communication. B Mohammad Gholami m.gholami@umz.ac.ir 1 Faculty of Engineering and Technology, University of Mazandaran, Babolsar, Iran