Statistical Reliability Analysis of NBTI Impact on FinFET SRAMs and Mitigation Technique Using Independent-Gate Devices Yao Wang, Sorin D. Cotofana Computer Engineering Laboratory, EEMCS Delft University of Technology Delft, 2628CD, the Netherlands Email: {Yao.Wang, S.D.Cotofana}@tudelft.nl Liang Fang School of Computer Science National University of Defense Technology Changsha, 410073, China Email: lfang@nudt.edu.cn Abstract—As planar MOSFETs is approaching its physical scaling limits, FinFET becomes one of the most promising alternative structure to keep on the industry scaling-down trend for future technology generations of 22 nm and beyond. In this paper, we propose a statistical model of Negative Bias Tempera- ture Instability (NBTI) tailored for FinFET SRAM Arrays. The model build upon an extension of the reaction-diffusion theory such that it can cover the natural variations encountered in nanoscale MOSFET circuits. Dynamic NBTI stress on SRAM cells is modeled by using stochastic input signals. A mitigation technology for minimizing the NBTI aging is also demonstrated by taking advantage of the independent-gate FinFET device structure using threshold voltage adjustment. We evaluated the impact of our proposal on the RAM stability by means of SPICE simulations with the BSIM-IMG Model for 22nm FinFET devices. Our simulations conducted at an accelerated temperature 125 ◦ C for 10 8 seconds (∼3 years) indicate that a V th compensation of 0.2V can almost preserve the WRITE and HOLD stability of the fresh device even after 3 years, while for the READ stability the compensation mechanism is less effective. However, the READ Static Noise Margin (SNM) experiences an insignificant decrease over the 3 years time span in the presence of a V th compensation, while without compensation it decreases by a x4 factor. Thus we can conclude that the proposed technique can improve the stability of SRAM array during its operational life, hence improve the performance and reliability of the system. I. I NTRODUCTION As technology scaling continues, the Integrated Circuits (IC) feature size has been driven into the physical limitation edge of conventional MOSFET device. In order to keep technology scaling down further, two major issues have to be properly addressed: (i) the excessive leakage power and (ii) the device/circuit reliability. Given that those have to be dealt with in the context of uncontrollable statistical process variations, the continuation of technology scaling seems to be more difficult than ever. In order to keep on the industry scaling-down trend, novel devices and structures were proposed as potential candidates to replace the conventional planar MOSFET device. Among the proposed novel devices, FinFET seems to be one of the most promising alternative structure for future technology gen- erations of 22 nm and beyond, owing to its fabrication process simplicity and good electrical characteristics [1]. Contributed to its device structure consisting of single/multiple vertical fin(s), the FinFET has better electrostatics on Short-Channel Effect (SCE), thus less static leakage current and power con- sumption. However, FinFET also experiences multiple tempo- ral degradations, e.g., Negative Bias Temperature Instability (NBTI), Hot Carrier Injection (HCI). In other words, on top of the spatial uncertainty caused by process variations, various temporal degradations hold back the feature size of technology from further scaling. In view of the previous argument, in this paper, we address the following aspects: (i) the modeling of the spatial and temporal reliability behavior of FinFET SRAM arrays under NBTI stress and (ii) the investigation of a mitigation method which can take advantage of the FinFET’s special device structure. NBTI is prominent in PMOS devices along the entire channel when negative gate-to-source voltage is applied, and it causes a threshold voltage (V th ) shift, which results in poor drive current and shorter device and circuit lifetime. Recent experimental investigations indicate that Multi-Gate FET devices with standard orientation exhibit worse NBTI than planar devices due to the higher availability of Si-H bonds at the (110) oriented fin sidewalls [2]. Depending on the electrical connection, i.e., shorted or isolated, between its gates, FinFET can operate at either on Shorted-Gate (SG) mode or Independent-Gate (IG) mode. In the shorted-gate operating mode the gates of the FinFET device are biased together to switch the channel conduction. In the independent- gate operating mode, one gate can be used to adjust the threshold voltage and the other gates are used to control the channel conduction. This offers a dynamic control-ability to mitigate or eliminate the damage caused by NBTI stress. In this line of reasoning, we first investigate the influence of stochastic input signal on long-term reliability under NBTI stress. Furthermore, the effect of random process variations on NBTI degradation, as well as the statistical characteristic of temporal degradation induced by NBTI are also discussed and analyzed. After that, we propose an NBTI mitigation