A Full Adder Implementation Using SET Based Linear Threshold Gates Casper Lageweg, Sorin Cotofana, Stamatis Vassiliadis Computer Engineering Laboratory, Electrical Engineering Department, Delft University of Technology, Delft, The Netherlands Email: Casper,Sorin,Stamatis @CE.ET.TUDelft.NL ABSTRACT In this paper we investigate single electron tunneling (SET) devices from the logic design perspective, using the SET tunnel junction’s ability to control the transport of in- dividual electrons. More in particular, we present the im- plementation of a Full Adder using SET threshold gates. First, we augment the threshold gates with an active buffer in order to overcome feedback effects which can appear in passive SET networks. Second, we derive the circuit pa- rameters for buffered SET threshold gates, and present the simulation results. Finally, we utilize the buffered thresh- old gates to build a Full Adder circuit, and verify the be- havior of the resulting circuit via simulation. 1. INTRODUCTION During the last decades the feature size of MOS based circuits has dramatically decreased. However, there have been reports [1] that the transistor itself cannot be shrunk beyond certain limits dictated by its operating principle. In order to ensure further feature size reduction, possible suc- cessor technologies with greater scaling potential such as Single Electron Tunneling (SET) [2, 3] are currently under investigation. Thus far, most studies carried out on SET based logic circuits approach the tunnel junction as a switch, using it to implement the SET equivalent of the MOS transis- tor [4, 5]. This has the advantage that existing CMOS transistor-based designs can easily be ported to SET tech- nology. The main disadvantage is that the current transport though an “open” transistor still consists of a large num- ber of individual electrons “dripping” through the tunnel junctions. This is obviously a far slower process then the transport of just one single electron through the same junc- tion, and consequently approaches that mimic the CMOS design style do not use the SET technology to its full po- tential. Our research focuses on the design of logic circuits in SET technology, using the SET tunnel junction’s specific behavior, i.e., the ability to control the transport of individ- ual electrons. The main idea behind our research is to per- form logic operations by transporting individual electrons to or from the output location under the control of the in- put(s). As part of this research we investigate in this paper the implementation of a Full Adder using SET threshold gates [6]. The main contributions can be summarized as follows. First, we augment the threshold gates with an ac- tive buffer in order to overcome feedback effects which can appear in passive SET networks. Second, we derive the circuit parameters for buffered SET threshold gates, and present the simulation results. Finally, we utilize the buffered threshold gates to build a Full Adder circuit, and verify the behavior of the resulting circuit via simulation. This paper is organized as follows: Section 2 briefly presents the SET background theory explaining the tun- neling behavior appearing in SET circuits. Section 3 in- troduced the SET linear threshold gate. In Section 4 we introduce the active buffer. In section 5 we present the im- plementation of buffered SET linear threshold gates and a Full Adder circuit, as well as the simulation results for the individual gates and the Full Adder. Finally, section 6 concludes our paper. 2. BACKGROUND A tunnel junction can be thought of as a leaky capacitor. The transport of charge through a tunnel junction is re- ferred to as tunneling, where the transport of a single elec- tron through a tunnel junction is referred to as a tunnel event. Electrons are considered to tunnel through a tunnel junction strictly one after another. The critical voltage across a tunnel junction is the voltage threshold needed across the tunnel junction to make a tunnel event through this tunnel junction possible. For calculating the critical voltage of a junction, we as- sume a tunnel junction with a capacitance of . The re- mainder of the circuit, as viewed from the tunnel junc- tion’s perspective, has an equivalent capacitance of . Given the approach presented in [7], we calculate the crit- ical voltage for the junction as: (1) 1 Generally speaking, if we define the voltage across a junction as , a tunnel event will occur through this tun- 1 In the equation above, as well as in the remainder of this discussion,