Testing of Timer Function Blocks in FBD Eunkyoung Jee, Seungjae Jeon, Hojung Bang, Sungdeok Cha Div. of Computer Science Korea Advanced Institute of Science and Technology Daejeon, Republic of Korea {ekjee,sjjeon,hjbang,cha}@dependable.kaist.ac.kr Junbeom Yoo Next Generation Mobile Equipment Team Samsung Electronics Co., Ltd. Suwon-si, Gyeonggi-do, Republic of Korea junbeom.yoo@samsung.com Geeyong Park, Keechoon Kwon I&C/Human Factors Division Korea Atomic Energy Research Institute Daejeon, Republic of Korea {gypark,kckwon}@kaeri.re.kr Abstract Testing for time-related behaviors of PLC software is important and should be performed carefully. We propose a structural testing technique on Function Block Diagram(FBD) networks including timer func- tion blocks. In order to test FBD networks including timer function blocks, we generate templates for timer function blocks and transform a unit FBD into a flow- graph using the proposed templates. We apply existing testing techniques to the generated flowgraph and de- scribe how the characteristics of timer function blocks are reflected in the testing process. By the proposed method, FBD networks including timer function blocks can be tested thoroughly without the intermediate code which was essential in the previous FBD testing. To demonstrate the effectiveness of the proposed method, we use a trip logic of bistable processor of digital plant protection systems which is being developed in Korea. 1. Introduction Testing of safety critical software is an indispensable step to assure software quality because the failures of safety critical software can cause serious damage to hu- man life or property. This work focuses on the programable logic con- troller(PLC) programs implemented by Function Block Diagram(FBD), one of the most widely used standard PLC programming languages. As existing analog sys- tems have been replaced by digital systems controlled by software, testing of digital control systems has be- come more important in nuclear power plant control systems. An FBD program is automatically compiled to PLC machine code and executed on PLC. In the previous case[1], functional testing on FBD has been done on the intermediate C source code transformed from an FBD network. We propose a structural testing method to test FBD networks including timer function blocks without having to generate the intermediate code. In [4], for the FBD testing, a unit FBD is transformed into a flowgraph and existing structural testing tech- niques are applied to the flowgraph. However, it did not address how timer function blocks could be tested. Because many PLC programs use timer function blocks and misused timer function blocks can cause serious er- rors, testing of timer function blocks is essential. In this paper, we extend work reported in [4] by defining flowgraph segment templates corresponding to the timer function blocks. The proposed method makes systematic structural testing for FBD networks including timer function blocks possible. This method also has an advantage that it can be applied to any FBD program, whatever its intermediate format is. We demonstrate our approach by applying it to a trip logic of Bistable Processor(BP) of Reactor Pro- tection Systems(RPS) which is being developed in Ko- rea Nuclear Instrumentation and Control System R&D Center(KNICS)[2]. We confirm that various errors in- cluding timer function block errors of a unit FBD can be found effectively by applying the proposed method. The remainder of the paper is organized as follows: