TECHNICAL PAPER Compact design of an MTJ-based non-volatile CAM cell with read/write operations Aminul Islam 1 • N. S. Ranjan 1 • Amit Krishna Dwivedi 1 Received: 4 August 2017 / Accepted: 15 June 2018 Ó Springer-Verlag GmbH Germany, part of Springer Nature 2018 Abstract This paper presents a novel design of a magnetic tunnel junction (MTJ) based content addressable memory (CAM) cell with low power dissipation and small-time delay. Magnetic properties of the spintronic device such as non-volatility, write endurance, small read–write delays, low switching current and so on, have been investigated in this paper. The proposed CAM cell design includes a simplified driver circuit to perform read/search and write operations using an optimum number of transistors. Performance parameters such as power dissipation, time-delay, power-delay product (PDP) and energy-delay product (EDP) of the proposed CAM cell are estimated and compared with the previously reported MTJ-based CAM cell already available in the literature. Simulation results obtained in this research work demonstrate that the proposed CAM cell successfully performs write operation at low voltages (up to 0.7 V). Write-time delay and the average power dissi- pation of the proposed CAM cell is found to be 0.3759 and 0.4499 less compared to the available MTJ-based CAM cell design. Apart from these, improvements in PDP and EDP of the proposed CAM cell is about 0.179 and 0.0639 compared to the previously reported MTJ-based CAM cell, respectively. Performance improvements are also obtained in terms of time delay and power consumption during the read/search operations of the proposed CAM cell. During the read operation with 0.8 V supply, the time-delay, the average power consumption, PDP and EDP of the proposed CAM cell was found to be 0.539, 0.649, 0.349 and 0.189 less compared to the MTJ-based CAM cell already reported in the literature, respectively. Simulation results have been exhaustively verified using SPICE. 1 Introduction Very-high-speed search engines are a predominant ele- mentary mechanism required extensively in a wide range of fields and applications. With the advent of technology, demands for compact and reliable search engines have been the focus of research recently and consequently, numerous developments can be observed in this field; the better ones replacing the previous systems. In the same spectrum of evolution, the inclusion of content addressable memory (CAM) cell is also one of the major developments in the search engine designs (Xu et al. 2010; Pagiamtzis and Sheikholeslami 2004). CAM systems being much faster than algorithmic approaches, are nowadays used for various search-intensive applications. However, available CAM systems are complex and require a large number of transistors in its designs. Conventionally, the search speed has always been inversely proportional to the size of a CAM cell circuitry. With a single clock system, a CAM is renowned for parallel-searching of the dataset, which cer- tainly is faster than or equal to the searching speed offered by the conventional search mechanisms. A CAM cell finds its application in image coding (Panchanathan and Goldberg 1991), parametric curve extraction (Meribout et al. 2000), Hough transformation (Nakanishi and Ogura 2000), Huffman coding (Komoto et al. 1993; Liu et al. 1994), Lempe–Ziv compression (Lee and Yang 1995), data packet forwarding and classification of Internet protocol in the network traffic routing and many other applications in signal processing technique. These applications demand a very high speed and compact CAM cell design with reduced power consumption. Figure 1 shows the system architecture of a typical CAM memory & Aminul Islam aminulislam@bitmesra.ac.in N. S. Ranjan be1062313@bitmesra.ac.in Amit Krishna Dwivedi a.k.dwivedi@ieee.org 1 Department of Electronics and Communication Engineering, Birla Institute of Technology, Mesra, Ranchi 835215, India 123 Microsystem Technologies https://doi.org/10.1007/s00542-018-4008-x