56 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 1, JANUARY 1999 A 500-MHz, 32-Word 64-Bit, Eight-Port Self-Resetting CMOS Register File Wei Hwang, Senior Member, IEEE, Rajiv V. Joshi, Senior Member, IEEE, and Walter H. Henkels Abstract—A two-write-port, six-read-port, 32 64-bit register file has been designed for 2.5-V 0.5- m CMOS technology, using primary self-resetting CMOS (SRCMOS) circuit techniques. The register cell are completely level-sensitive scan design test com- patible. The fabricated register file occupies an area of 1.84 1.55 mm , and the cell size is 21.6 30 m . The high-performance register file is implemented in a multiblock structure consisting of subarrays and associated multiplexing circuits. For a given read port, the outputs of all multiplexer circuits are dotted together to form a single global output. A quasi-global approach is used for reset pulse generation and timing control circuits to reduce area overhead. The output pulse width is controlled by a chopper circuit. The write-port operation is achieved by the combination of static data input and dynamic control circuits. The write-path circuits employ the advantages of the input isolation technique. Individual write-enable pulses applied to respective input ports of a multiport register-file cell are effective to establish a priority among those input ports. The present design provides an effective input isolation/decoupling circuit technique that allows the input pulse widths to vary over a wide range. This allows the write operation to be insensitive to control pulse widths, resulting in an effective input isolation scheme. Testing has shown all eight ports to be functional. The measured read access time was 1.1 ns, and read operation has been obtained at cycle times as short as 1.9 ns. The register file has been shown to be tolerant to a very wide range of input pulse widths yet delivers tightly controlled outputs. Index Terms—CMOS integrated circuits, dynamic logic circuit, high-speed integrated circuits, integrated circuit design, micro- processor, registers. I. INTRODUCTION G ENERAL-purpose register files are basic building blocks of all microprocessors. The register-file transfer op- erations are directly controlled by the microprocessor after instructions are decoded. The register file is conducted at microprocessor speed, usually in one clock cycle. Therefore, a high-performance microprocessor requires a high-performance register file. For best performance, register files have only a few ports, e.g., three typically employ dual-rail writing and differential sense-amp reading of the memory cells [1], [2]. The advent of superscalar architectures for microprocessors has created the need for register files to have many ports, so that several units can have simultaneous access [3]–[7]. Such multiporting is at odds with the universal goals of high density, high performance, and ease of testing. High-density Manuscript received October 20, 1997; revised May 6, 1998. W. Hwang and R. J. Joshi are with the IBM Research Division, T. J. Watson Research Center, Yorktown Heights, NY 10598 USA. W. H. Henkels, deceased, was with the IBM Research Division, T. J. Watson Research Center, Yorktown Heights, NY 10598 USA. Publisher Item Identifier S 0018-9200(99)00398-4. multiporting favors abandoning dual-rail in favor of single- ended reading and writing. However, single-ended operation typically makes high performance more difficult to achieve, and as such the choice of a single-ended sensing scheme is a key consideration in design [8]–[10]. Another issue in very-large-scale integrated circuit design is that of testing the millions of transistors on a chip. Typically, large memory arrays allow an overhead for array built-in self-test (ABIST) circuity. For small arrays, such as register files, the overhead of an ABIST is more significant for performance and area, and thus is less acceptable. With this background, we have set out to design a two- write/six-read-port, 32-word 64-bit register file that is fast, dense, and readily testable in 2.5-V, 0.5- m CMOS technology [11]. Our approach employs self-resetting CMOS (SRCMOS) dynamic circuits [12]. Special attention has been paid to insuring design robustness with regard to variations in input pulse width. The testing issue has been dealt with up front by making the memory cells totally level-sensitive scan design (LSSD) compatible and by applying the SRCMOS diagnostic testing methodology. No additional circuity is required. In Section II, the multiport architecture features and register cell are described. The register file is implemented in a multi- blocks structure consisting of four quadrants and associated multiplexing circuits. For a given read port, the outputs of all multiplexer circuits are dotted together to form a single global output. The multiplexer circuits are distributed and integrated into the register cells. The register cells arranged as such contain an extra latch, a pass transfer gate, and control arranged so that the file can be fully tested via LSSD. In Section III, high-speed SRCMOS dynamic circuits for read- and write-port paths are presented. New circuit techniques, which include the output-pulse chopping circuit, input isolation, and associated dynamic-to-static conversion latch for dataflow, are considered. Special attention has been paid to designing the reset pulse generation and timing control blocks. Single-ended sensing is efficiently accomplished via partitioned self-resetting multiplexers. This partitioning im- plies duplication of some circuits, hence the compactness of the associated physical layouts is crucial to the success of the design. The fabricated register file and measurement results are presented in Section IV. The summary and conclusion of this paper is given in Section V. II. ARCHITECTURE AND REGISTER CELL The main components—read and write ports, input/output, and a total array architecture—are shown in Fig. 1. The figure 0018–9200/99$10.00  1999 IEEE