0018-9340 (c) 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TC.2015.2455978, IEEE Transactions on Computers SUBMITTED TO IEEE TRANSACTIONS ON COMPUTERS, DEC. 2014 1 A Hybrid Non-Volatile Cache Design for Solid-State Drives Using Comprehensive I/O Characterization Mojtaba Tarihi, Hossein Asadi, Alireza Haghdoost, Mohammad Arjomand, and Hamid Sarbazi-Azad Abstract—The emergence of new memory technologies provides us with opportunity to enhance the properties of existing memory architectures. One such technology is Phase Change Memory (PCM) which boasts superior scalability, power savings, non-volatility, and a performance competitive to Dynamic Random Access Memory (DRAM). In this paper, we propose a write buffer architecture for Solid-State Drives (SSDs) which attempts to exploit PCM as a DRAM alternative while alleviating its issues such as long write latency, high write energy, and ﬁnite endurance. To this end and based on thorough I/O characterization of desktop and enterprise applications, we propose a hybrid DRAM-PCM SSD cache design with an intelligent data movement scheme. This architecture manages to improve energy efﬁciency while enhancing performance and endurance. To study the design trade-offs between energy, performance, and endurance, we augmented Microsoft’s DiskSim SSD model with a detailed hybrid cache using PCM and DRAM parameters from a rigorous survey of device prototypes. We study the design choices of implementing different PCM and DRAM arrays to achieve the best trade-off between energy and performance. The results display up to 77% power savings compared to a DRAM cache and up to 26% reduction in request response time for a variety of workloads, while greatly improving disk endurance. Keywords—SSD cache, Hybrid memory, Phase change RAM. I. I NTRODUCTION O VER the past decade, NAND ﬂash-based Solid-State Drives (SSDs) have shown promising ability in addressing the technical issues of legacy HDD based storage systems such as high energy consumption, low reliability, and poor performance on random workloads. However, fully exploiting the performance, energy, and reliability advantages of this tech- nology requires overcoming the challenging issues posed by its underlying technology; the ﬂash technology has ﬁnite endurance and its access and erase operations function at mismatched granularities and have very different latencies. As a result, SSD controllers implement the Flash Translation Layer (FTL) as a ﬁrmware which hides the internal implementation details and presents the drive as a block device to the host computer. As erase operations are slow and energy intensive, FTLs use log- based approaches [1], [2] or other mapping schemes [3], [4], [5] to reduce the number of erase operations and perform wear- leveling which tries to even the wear-out of ﬂash memory cells. An SSD controller resides between the host interface and ﬂash memories and implements the required functionalities such as FTL. The FTL functionalities can be implemented as soft- ware [6] or be synthesized from Hardware Description Language (HDL) code as hardware [7]. Most SSDs also come with on-board Dynamic Random Access Memory (DRAM) to store cached disk data and FTL data structures, which can signiﬁcantly reduce the amount of writes committed to ﬂash if data exhibits locality in write operations. A cache can also greatly reduce response time for write operations since acknowledgment can be sent as soon as the data is written to the cache memory, while the slow writes to ﬂash memories will be performed in the background. Due to the long latencies of write and erase opera- tions, cache memory can be highly effective in improving SSD performance. Thus, in order to improve or at least maintain the cache hit ratio with the increased SSD capacity, designers have aggressively increased the cache size in recent prototypes [8], [9], [10]. The empirical evaluations of modern SSDs under desktop applications show that SSDs’ front-end logic is idle in most of run time [11]. Hence, the standby power of this logic, leakage and refresh power of DRAM array are the key contributors to the overall power of SSD such that using larger DRAM caches signiﬁcantly increases overall power consumption due to increased leakage, refresh power, and per-operation energy consumption. The impact of this effect will be especially evident when storage arrays at large-scale installations composed of thousands of disks are considered. Furthermore, larger DRAM caches are increasingly constrained by data integrity issues. Indeed, uncommitted data furthers the dangers of power loss, requiring the storage system or SSDs to include backup batteries or capacitors to commit changes to ﬂash. Worse yet, it has been demonstrated that even some of these enterprise SSDs lose data upon power outage in the presence of battery backup [12]. To address the limitations of DRAM, emerging non-volatile memory technologies such as Phase Change Memory (PCM) have been suggested as a candidate to replace DRAM in the main memory [13], [14], [15]. PCM is one of the most promising non-volatile memories, which instead of using electrical charges to store information, stores bit values with the physical state of a chalcogenide material (e.g., Ge 2 Sb 2 Te 5 , i.e. GST). Under different current amplitudes and durations, the material can be formed into either an amorphous or crystalline state with completely different levels of resistivity. Due to non-volatility, high density, and fast read access of PCM, the last few years have seen a large body of research attempting to evaluate the potential of PCM as a DRAM alternative for main memory [13], [14], [15]. However, to the best of our knowledge, none of these studies have tried to use PCM in the cache memory of SSDs. In this work, we introduce and investigate a novel hybrid SSD cache architecture composed of DRAM and PCM memory. The motivation for such an architecture originates from key trade-offs of using these technologies together. While PCM read latency and energy is fairly competitive to DRAM, PCM write operations are more costly in terms of both latency and energy. Also, the durability of PCM cells, while better than NAND ﬂash cells, is