Design for MOSIS Educational Program (Research) FABRICATION REPORT A low power adaptive integrated circuit for the detection of time delay in digital signals Prepared by: Franco Martin-Pirchio, Alfonso Chac ´ on-Rodr´ ıguez 1 , Pedro Juli´ an 2 , Pablo Mandolesi 3 Institution: Departamento de Ingenier´ ıa El´ ectrica y Computadoras, Universidad Nacional del Sur, Av. Alem 1253, Bah´ ıa Blanca, Argentina Date of Submission: March 5th, 2007 Design Number: 77260 Fab-ID: T73ZAC 1 Introduction The objective of this proposal was to fabricate an integrated circuit for the low power calculation of the delay between two digital signals with central frequencies in the range [20, 1000] Hz. The circuit is intended for bearing estimation sensor networks, and a previous alternative implementation is cited in [1] and [2]. The need for a very low power architecture, yet still highly accurate for field tracking, prompted the search for a better implementation. Figure 1: Delay estimation by the cross-correlation method, as proposed in [2] Juli´ an et al [2] proposed a variation of the cross-correlation algorithm for bearing estimation. They showed that a discrete correlation can be achieved with a 1-bit quantization of the signals, with a 1 On leave from Instituto Tecnol´ ogico de Costa Rica 2 P. Juli´ an is also with CONICET, Av. Rivadavia 1917, Bs. As., Argentina 3 P. S. Mandolesi is with CIC, Pcia. Buenos Aires, Argentina 1