TEM CHARACTERIZATION OF GaAs PIN DIODES AT LOW TEMPERATURES ON Si SUBSTRATES G. ARAGON, S.I. MOLINA, L. GONZALEZ*, Y. GONZALEZ*, J.V. ANGUITA*, F. BRIONES* and R. GARCIA Departamento de Ciencia de los Materiales e Ingenieria Metali~rgica y Qufmica Inorgdnica. Universidad de Cddiz. Apdo 40, Puerto Real, 11510-C.diz. Spain. *Centro Nacional de Microelectr6nica. Serrano 144, 28006-Madrid. Spain. ABSTRACT GaAs pin and nip diodes have been grown by Atomic Layer Molecular Beam Epitaxy at 350 0 C on p-type and n-type (001) Si substrates respectively. These devices present different electrical characteristics. TEM characterization of these structures shows an asymmetric planar defect distribution whose orientation depends on the type of doping introduced in the GaAs layer immediately grown on the Si substrate. These results can be explained taking into account that the dissociation of dislocations depends both on the polarity of the dislocation and the doping type of the epilayer. INTRODUCTION The sucessfull assessment of an actual III-V on Si technology is strongly conditioned to a temperature reduction of the entire growth process, from the Si surface preparation to the epitaxial growth itself, in order to compatibilize III-V and CMOS based on Si technologies. Epitaxial growth at low temperatures (Ts<400 0 C) is then mandatory for monolithic integration purposes. However, device performance will be influenced by the kind and density of defects which appear during low growth temperature to accommodate the large lattice mismatch between the III-V compound and the Si substrate. Besides the growth temperature, the density and type of doping impurities can also affect the lattice mismatch relaxation process. In fact, we have observed different electrical characteristics on GaAs pin diodes, grown at low temperature by Atomic Layer Molecular Beam Epitaxy (ALMBE), on p-type Si substrates compared to nip diodes grown on n-type Si substrates. In this paper we present a TEM study of low growth temperature fabricated GaAs pin diodes on Si substrates in order to assess the influence of the defect structure on the electrical behaviour of such devices. EXPERIMENTAL The samples were grown by ALMBE[1] at Ts=350 0 C on (001) doped Si substrates 20 off toward [110]. The samples consist of an unintentionally doped GaAs layer sandwiched between two GaAs layers doped with Si and Be (n and p respectively) at concentrations of 2 1018 atoms/cm 3 . Two kinds of structures have been studied, one of them consists of a p-Si substrate/p+-i-n+ GaAs and the other of a n-Si substrate/n+-i-p+ GaAs (figure 1). From this point we will label to the samples grown on n-type and p-type Si substrate as NO and P0 respectively. Some structures 97 Mat. Res. Soc. Symp. Proc. Vol. 326. ©1994 Materials Research Society