Selective Incorporation of Colloidal Nanocrystals in Nanopatterned SiO 2 Layer for Nanocrystal Memory Device Il Seo, a Do-Joong Lee, b Quanli Hu, a Chang-Woo Kwon, b Kipil Lim, b Seung-Hyun Lee, b Hyun-Mi Kim, b Yong-Sang Kim, a Hyun Ho Lee, c Du Yeol Ryu, d Ki-Bum Kim, b and Tae-Sik Yoon a,z a Department of Nano Science and Engineering and c Department of Chemical Engineering, Myongji University, Gyeonggi 449-728, Korea b Department of Materials Science and Engineering, Seoul National University, Seoul 151-742, Korea d Department of Chemical and Biomolecular Engineering, Yonsei University, Seoul 120-749, Korea CdSe colloidal nanocrystals with a size of 5 nm were selectively incorporated in SiO 2 nanopatterns formed by a self-assembled diblock copolymer patterning through a simple dip-coating process. The selective incorporation was achieved by capillary force, which drives the nanocrystals into the patterns during solvent evaporation in dip-coating. The capacitor structures of an Al-gate/ atomic layer deposition–Al 2 O 3  27 nm/CdSe 5 nm/patterned SiO 2  25 nm /p-Si substrate were fabricated to characterize the charging/discharging behavior for a memory device. The flatband voltage shift was observed by a charge transport between the gate and the nanocrystals. It demonstrates the colloidal nanocrystal application to a memory device through selective incorporation in regularly ordered nanopatterns by a simple dip-coating process. © 2009 The Electrochemical Society. DOI: 10.1149/1.3271025 All rights reserved. Manuscript submitted September 14, 2009; revised manuscript received October 15, 2009. Published December 17, 2009. Memory devices with nanocrystals NCs embedded in a gate dielectric layer have been actively investigated for their improved scalability and retention properties, which also render a possible low voltage operation, thanks to the structure having discrete charge storage nodes. 1-3 To form isolated NCs embedded in a dielectric layer, various approaches have been employed, including thin-film deposition by chemical vapor deposition, 4,5 atomic layer deposition ALD, 6 and physical vapor deposition, 7 during which NCs are formed at the nucleation stage of thin films. Also, ion implantation and subsequent annealing for precipitation of NCs 8 and oxidation of SiGe for Ge-rich NC formation 9,10 have been reported. Though NCs can be successfully formed within a dielectric layer via the above-mentioned approaches, it is still challenging to achieve a uniform array of NCs with identical sizes and densities, which is crucial to realizing a uniform device performance. To this end, nanopatterning with a self-assembled diblock copolymer has been employed, where NCs are selectively formed in the patterns. 11,12 Black et al. 11 used a polystyrene-b-methyl- methacrylatePS-b-PMMA diblock copolymer as an etching mask of a SiO 2 tunneling layer and subsequently formed Si NCs by chemical vapor deposition and an etch-back process, which left the Si NCs only inside the patterns as being isolated from each other. Also, Shahrjerdi et al. 12 used the same PS-b-PMMA diblock copoly- mer to pattern a structure of SiO 2 /polyimide /SiO 2 multilayers for a lift-off process. Through the evaporation of Ni and a subsequent lift-off process by dissolving polyimide to remove the Ni layer on top of the SiO 2 layer, Ni NCs were finally left on the bottom of the SiO 2 patterns as being replicated from the diblock copolymer pat- tern. This selective formation of NCs on nanopatterns is a straight- forward method to form the uniform array of NCs. In this study, we employed the nanopattering of a SiO 2 dielectric layer with a self-assembled PS-b-PMMA diblock copolymer and selectively filled the patterns with colloidal CdSe NCs by a dip- coating process. This is a very simple process that consists of the patterning of a tunneling dielectric layer and subsequent dip-coating. Also, the structures, having single or multiple layers of various NCs, can be easily constructed through dip-coating with various colloidal NC solutions. Thin films of the PS-b-PMMA diblock copolymer were used for the patterning of the SiO 2 layer with a thickness of 25 nm on a p-Si substrate. Before coating PS-b-PMMA, a polymer brush layer with a thickness of 5 nm was coated to induce the cylindrical micro- domains oriented normal to the surface with a hexagonal pattern. Then, a 30 nm thick PS-b-PMMA layer was spin-coated and an- nealed at 170°C for 24 h to form the hexagonally self-assembled cylindrical patterns. 13 The copolymer pattern was transferred to the underlying SiO 2 layer by selectively removing the PMMA block and by reactive ion etching of the SiO 2 layer. The etched hole patterns have a diameter of about 20 nm with an 40 nm center-to-center distance, which corresponds to a pattern density of 7  10 10 cm -2 . The substrates were dipped into a CdSe colloidal NC solution, were withdrawn with a speed of 0.01 mm/s after a duration time of 1 min in the solution, and were dried in air at room temperature to deliver NCs into the patterns. The CdSe NCs with a diameter of approxi- mately 5 nm, coated with a thin ZnS layer and trioctylphosphine oxide TOPO as a surfactant, were used as purchased from Nanosquare Inc. The CdSe NC had a composition of Cd:Se = 6:4, and the overcoating ZnS layer had a composition of Zn:S = 7:3, which were analyzed using inductively coupled plasma atomic emis- sion spectroscopy. The NCs were dispersed in octane with a concen- tration of an order of 10 16 /mL. The selective deposition of NCs inside the patterns was analyzed using scanning electron microscopy SEM, Carl Zeiss LEO SUPRA 55 and transmission electron mi- croscopy TEM, JEOL JEM-3000F. For a clear observation of NCs, a high angle annular dark field HAADF imaging technique was also used for the TEM analysis. To characterize the charging and discharging behavior, the ca- pacitor structure was fabricated by depositing a 27 nm thick Al 2 O 3 layer by ALD after dip-coating for CdSe NC deposition. ALD-Al 2 O 3 was deposited using trimethylaluminum and H 2 O for 250 reaction cycles at 300°C. During the ALD of the Al 2 O 3 layer, some remaining surfactants on the surface were expected to desorb because the surfactants attached on the colloidal NC surface were readily desorbed above 200°C. 14,15 Then, the top Al gate was formed with a 200 m diameter through evaporation and patterning by optical lithography and wet etching processes. The charging and discharging behavior was analyzed using high frequency capacitance–voltage  C-V characteristics with a maximum sweep voltage from -30 to 30 V and a frequency of 1 MHz with a 25 mV oscillation using an Agilent 4284A precision LCR meter. The pro- cedure of the selective formation of NCs in nanopatterns and the device structure for the C-V analysis are schematically illustrated in Fig. 1. Figure 2 is the plan-view SEM micrograph of CdSe NCs in SiO 2 hole patterns. The CdSe NCs are selectively incorporated into al- most entire hole patterns. As previously reported, the colloidal NCs can be selectively deposited inside the patterns by the capillary- z E-mail: tsyoon@mju.ac.kr Electrochemical and Solid-State Letters, 13 3 K19-K21 2010 1099-0062/2009/133/K19/3/$28.00 © The Electrochemical Society K19 ) unless CC License in place (see abstract). ecsdl.org/site/terms_use address. Redistribution subject to ECS terms of use (see 115.145.155.16 Downloaded on 2014-11-26 to IP