Self-repairing adder using fault localization Muhammad Ali Akbar, Jeong-A Lee ⇑ Computer System Lab, Department of Computer Engineering, Chosun University, South Korea article info Article history: Received 31 October 2013 Received in revised form 20 January 2014 Accepted 20 February 2014 Available online xxxx Keywords: Self-checking adder Carry-select adder Fault localization Self-repairing adder Multiple faults abstract In this paper we propose an area-efficient self-repairing adder that can repair multiple faults and identify the particular faulty full adder. Fault detection and recovery has been carried out using self-checking full adders that can diagnose the fault based on internal functionality, independent of a fault propagated through carry. The idea was motivated by the common design problem of fault propagation due to carry in various approaches by self-checking adders. Such a fault can create problems in detecting the particular faulty full adder, and we need to replace the entire adder when an error is detected. We apply our self-checking full adder to a carry-select adder (CSeA) and show that the resulting self-checking CSeA consumes 15% less area compared to the previously proposed self-checking CSeA approach without fault localization. After observing fault localization with reduced area overhead, we utilize the self-checking full adder in constructing a self-repairing adder. It has been observed that our proposed self-repairing 16-bit adder can handle up to four faults effectively, with an 80% probability of error recovery compared to triple modular redundancy, which can handle only a single fault at a time. Ó 2014 Elsevier Ltd. All rights reserved. 1. Introduction Advanced microelectronic technologies have allowed current digital systems to become more vulnerable to faults. It has been observed that the problem of single-event upset in digital systems has become more prominent with the increasing complexity of system on a chip, along with decreasing clock cycles to obtain high operating frequency [1,2]. The design of a compact circuit on a chip is advantageous in terms of noise but creates various problems in terms of reliability [3,4]. Researchers agree that reduction in hard- ware size will increase hardware failures in future processors [5]. Thermal cycling, dielectric behavior and biasing of digital inte- grated circuits have also caused many transient and permanent faults [6]. In order to deal with the above-mentioned problems, the con- cepts of self-checking and fault tolerance have been introduced. A system will be fault secure if it remains unaffected by a fault or if it indicates a fault as soon as it occurs [7]. A system will be self-test- ing if it produces a non-coded output in response to every generated fault [8]. A system will be totally self-checking (TSC) if it is both fault secure and self-testing [7]. The concept of TSC is used in different applications, like self-healing networks [9], self-checking arithme- tic logic units (ALUs) [10], etc. Self-checking usually emphasizes the detection of faults and overlooks the overhead associated with fault recovery. Most of the self-checking approaches require re-execution of instructions for fault recovery [11]. However, the re-execution process affects system performance because all operations connected directly or indirectly to the faulty module should be re-executed. Further- more, re-execution cannot guarantee fault recovery, especially if there is a permanent fault or wear-out problem. Therefore, on-line detection and self-repairing is required in a highly dependable sys- tem architecture [12]. In digital system designs, the adder has a wide variety of appli- cations [13]. In the past, many approaches have been adopted to introduce self-checking in adder circuits either by hardware- or time-based redundancy. These approaches can detect an error without indicating its exact location because of fault propagation due to carry. In this paper, we propose a new self-checking and self-repairing full adder in which the faulty full adder module can be identified. Self-checking and repair has been attained using the observed relationship between Sum and Carry-out. The Sum and Carry-out bits of a full adder will be equal to each other when all three inputs are equal. The Sum and Carry-out bits will be com- plemented when any of the three inputs are different. A carry-select adder (CSeA) pre-computes Sum bits using two adders with complemented values of the initial C in , and the final Sum bit will be generated after receiving the actual value of the C in . The presence of two adders is advantageous for introducing a self-checking ability. We first apply our self-checking full adder http://dx.doi.org/10.1016/j.microrel.2014.02.033 0026-2714/Ó 2014 Elsevier Ltd. All rights reserved. ⇑ Corresponding author. Tel.: +82 106851 2207; fax: +82 062 233 6896. E-mail addresses: mali.neduet@gmail.com (M.A. Akbar), jalee@chosun.ac.kr (Jeong-A Lee). Microelectronics Reliability xxx (2014) xxx–xxx Contents lists available at ScienceDirect Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel Please cite this article in press as: Akbar MA, Lee J-A. Self-repairing adder using fault localization. Microelectron Reliab (2014), http://dx.doi.org/10.1016/ j.microrel.2014.02.033