VOL. 11, NO. 15, AUGUST 2016 ISSN 1819-6608 ARPN Journal of Engineering and Applied Sciences ©2006-2016 Asian Research Publishing Network (ARPN). All rights reserved. www.arpnjournals.com 9364 DESIGN OF LOW POWER LOW VOLTAGE CMOS AMPLIFIERS IN SUBTHRESHOLD REGION L. Premalatha and P. Kavi Priya Department of Electronics and Communication Engineering, Sathyabama University, Tamil Nadu, India E-Mail: lpremalatha@gmail.com ABSTRACT The growing demand of portable electronics equipment makes the circuit designer think about low power low voltage integrated circuit design. The major drawback on implementing strong inversion low-voltage CMOS circuits is the threshold voltage which does not scale down as the same rate as compared to the power supply. Hence the design of electronic circuits operated in subthreshold region has become an absolutely necessary feature in order to provide efficient benefits by technology scaling. This Project focuses on the weak inversion design of low power low voltage Inverter, Nand gate, common source amplifier, Differential amplifier and Operational Transconductance Amplifier (OTA). The CMOS OTA is designed in 350 nm CMOS TSMC process technology and BSIM 3v3 SPICE model and obtained 66db gain, 61 degree phase margin with 163nW power consumption by applying 0.9V supply voltage. In design of CMOS OTA TANNER EDA TOOL is used. Keywords: amplifiers, digital logic gates, frequency compensation, medium performance, sub-threshold region, ultra low power. INTRODUCTION Many researches in balancing the trade-off between power and performance have been done in the average performance, average power region of the design spectrum. Still, not more studies have been done at the two extreme ends of the design spectrum, at one end namely the ultra-low power with acceptable performance and at the other end high performance with power within limit [12]. To achieve the ultra-low power requirement one solution is to operate Transistors in sub-threshold region (supply voltage less than the threshold voltage (Vth)) of the transistor) [11]. In this paper, we investigate sub- threshold region for ultra-low-power applications. The performance characteristics of inverter and Operational Transconductance Amplifier operating in the sub- threshold region have been discussed using 350nm TSMC CMOS technology in Tanner circuit simulation tool. More recently, design of digital and analog circuits was investigated with transistors operated in the weak inversion region, in such a technique the sub threshold undesired leakage current of the device is used for computation. Significant power savings can be obtained for low to medium with ten to hundreds of megahertz frequency of operation applications [12]. Hearing aid devices are clearly one of the most appropriate application areas for subthreshold logic since ultra-low-power consumption requirement takes first priority, while the clock rate is nearly in the kHz range [17]. SUBTHRESHOLD REGION Generally when a MOS transistor in saturation region within any analog or digital circuit, we anticipated that the transistor is turned off (drain to source current is zero) when the transistors gate source voltage is below threshold voltage of that transistor. This region is known as Subthreshold region also known as weak inversion region. Subthreshold current In ideal case current flows from drain to source is zero in subthreshold region. But, exactly below the threshold the drain current is exponentially proportional to the gate to source potential [11]. This current is known as subthreshold current and is given as below equation [17].  ஽ =  ௣௘௖   ቀ ௏ ಸೄ − ௏ ೅ಹ ௏ ೅ ቁ [ͳ −   ቀ− ௏ ೄ ௏ ೅ ቁ] (1) Where  ௣௘௖ = ʹ ௑ ௐ    2 (2) Where  ு is the threshold voltage of the transistor,  ௌ is the gate voltage,  ஽ௌ is the drain voltage, n is subthreshold factor and is given by ቀ = ͳ + ஼  ஼  ቁ (3)  ௑ is the oxide capacitance and  ௗ is depletion capacitance V T is the thermal potential [  =  ௤ ] (4)  is Boltzmann constant,  is room temperature in Kelvin [300K], q is charge of electron[17]. If  ஽ௌ >4  then exp −V D౏ V ౐ ≪ͳ, since e−4≌ Ͳ.Ͳͳ8. The last term in equation (1) is approaches equal to one, which can be ignored. So, the expression for drain current then,  ஽ =  ௣௘௖  ቀ ௏ ಸೄ − ௏ ೅ಹ ௏ ೅ ቁ (5)