IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 1, JANUARY 2007 67 Low-Power-Design Space Exploration Considering Process Variation Using Robust Optimization Ashish Srivastava, Member,IEEE, Tejasvi Kachru, Student Member, IEEE, and Dennis Sylvester, Senior Member, IEEE Abstract—Increasing levels of process variation in current process technologies make it extremely important that design and process decisions be made while considering their impact. This paper presents a convex-optimization-based approach to select values of supply voltages, threshold voltages, and oxide thick- nesses to minimize power dissipation in a simplified abstraction of multi-Vdd/Vth/Tox CMOS designs while considering process vari- ation. The authors use this probabilistic approach to perform op- timization of different statistical parameters of power dissipation (e.g., mean or high percentile points) and quantify the impact of rising process variations on these power-minimization techniques. Index Terms—Power minimization, robust optimization, vari- ability, yield allocation. I. I NTRODUCTION P OWER consumption has become a top priority in modern circuit design. Multiple supply and threshold voltages have been shown to be extremely effective in reducing total power dissipation. Previous implementations using multiple supply and threshold voltages have shown impressive reductions in both the dynamic and subthreshold leakage power of a design [1], [2]. The effectiveness of multiple-supply-voltage (Vdd) techniques was first shown to scale poorly in [3]. However, the study in [4] showed that using multiple supply and threshold voltages (Vth) in conjunction is very effective in achieving large power savings in sub-1-V technologies. In particular, the guideline from the study in [4] that a second supply voltage (Vdd 2 ) should be approximately half that of the higher supply voltage (Vdd 1 ) to minimize power, given a dual-Vth process, was confirmed on actual circuit benchmarks in later work [29]. This result of the study in [4] was counter to previous design experience of single-Vth and dual-Vdd circuits; therefore, the corroboration by applying dual-Vdd and dual-Vth optimization to actual circuits gives strong support to the idea that correct Manuscript received April 8, 2005; revised November 24, 2005 and May 3, 2006. This work was supported in part by the MARCO/DARPA Gigascale Silicon Research Center, in part by the Semiconductor Research Corporation, and in part by Intel. This paper was recommended by Associate Editor F. N. Najm. A. Srivastava was with the Department of Electrical Engineering and Com- puter Science, University of Michigan, Ann Arbor, MI 48109 USA. He is now with the Intel Corporation, Hillsboro, OR 97124 USA. T. Kachru was with the Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI 48109 USA. He is now with Advanced Micro Devices, Sunnyvale, CA 94088 USA. D. Sylvester is with the Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI 48109 USA. Digital Object Identifier 10.1109/TCAD.2006.882491 and valuable trends and design guidelines can result from this high-level abstract representation of a complex circuit. Furthermore, recent announcements of sub-100-nm process technologies have described the availability of multiple oxide thicknesses (Tox) to combat gate-oxide tunneling leakage [15], [16]. Since gate-oxide leakage is a very strong function of Tox, this component of leakage has become prominent with ultrathin oxides below 15 Å. The International Technology Roadmap for Semiconductors (ITRS) projects that gate leakage and subthreshold leakage are comparable at room temperature in modern processes through 2008 [17]. Similar to multi-Vth or multi-Vdd techniques, the use of multiple oxide thicknesses in a design can allow designers to reduce gate leakage in noncritical paths at the expense of slower devices/gates. In particular, the study in [14] describes a sensitivity-based methodology to use dual-Tox to reduce total gate leakage of a circuit. The selection of appropriate values for the supply and thresh- old voltages to minimize power dissipation has been previ- ously investigated under deterministic conditions [3], [4]. In [3], the authors propose an approach to select optimal supply and threshold voltages in either multiple-Vdd or multiple-Vth designs by minimizing dynamic or static power, respectively. This approach is extended in [4] to the selection of both Vth and Vdd and considers optimization of total power in multi-Vdd/Vth systems. All these approaches ignore process variations and perform deterministic power optimization only. Gate leakage is also ignored in these works; therefore, gate- leakage minimization in multi-Tox processes is not consid- ered. Recently, the study in [19] proposed a probabilistic approach to consider variations in threshold voltage. This ap- proach makes a number of assumptions while formulating the problem, such as uniform yield allocation, and neglects the impact of low-Vth variability on delay, as will be discussed in Section II. The rise in inherent process variability with technology scaling has been shown to have a tremendous impact both on the power dissipation and performance of current designs. The study in [5] shows a 20× variation in leakage power for a 1.3× variation in delay between fast and slow dies. Due to the inverse relationship between power and delay, most of the fastest chips in a lot are found to have unacceptable power dissipation and vice versa. In addition, low-Vth devices exhibit increased sensitivity to variations in their leakage power due to exacerbated drain-induced barrier lowering (DIBL) effects [6]. Hence, any design technique employing low-Vth devices that ignores the impact of variability may adversely impact the parametric yield of the design. 0278-0070/$25.00 © 2007 IEEE