This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1 Gain-Cell Embedded DRAMs: Modeling and Design Space Andrea Bonetti , Student Member, IEEE, Roman Golman, Student Member, IEEE, Robert Giterman, Student Member, IEEE, Adam Teman , Member, IEEE, and Andreas Burg , Member, IEEE Abstract—Among the different types of dynamic random- access memories (DRAMs), gain-cell embedded DRAM (GC-eDRAM) is a compact, low-power, and CMOS-compatible alternative to conventional static random-access memory (SRAM). GC-eDRAM achieves high memory density, as it relies on a storage cell that can be implemented with as few as two transistors and that can be fabricated without additional process steps. However, since the performance of GC-eDRAMs relies on many interdependent variables, the optimization of the performance of these memories for the integration into their hosting system, as well as the design investigation of future GC-eDRAMs, proves to be highly complex tasks. In this context, modeling tools of memories are key enablers for the exploration of this large design space in a short amount of time. In this article, we present GC-eDRAM modeling tool (GEMTOO), the first modeling tool that estimates timing, memory availability, bandwidth, and area of GC-eDRAMs. The tool considers parameters related to technology, circuits, and memory architecture, and it enables the evaluation of architectural transformations as well as advanced transistor- level effects, such as the increase in the access delay due to the deterioration of the stored data. The timing is estimated with a maximum deviation of 15% from postlayout simulations in a 28-nm FD-SOI technology for different memory sizes and architectures. Moreover, the measured random cycle frequency of a GC-eDRAM fabricated in a 28-nm CMOS bulk process is estimated with a 9% deviation when considering 6-sigma random process variations of the bitcells. The proposed GEMTOO modeling tool is used to show the intricacies in design optimization of GC-eDRAMs, and based on the results, optimal design practices are derived. Index Terms— Computer-aided design, embedded dynamic random-access memory (DRAM), gain cell (GC), GC-eDRAM modeling tool (GEMTOO), memory design, memory organiza- tion, modeling tool. I. I NTRODUCTION T HE last decade of computing has been driven by data- intensive applications, which have raised the need for large-capacity memories. As a result, the silicon area of many microprocessors and system-on-chip (SoC) designs is dominated by embedded memories [1]–[4], especially when conventional six-transistor (6T) static random access memory Manuscript received July 26, 2019; revised October 14, 2019; accepted November 3, 2019. The work of A. Teman was supported by the German- Israeli Foundation for Scientific Research and Development (GIF). (Corre- sponding author: Andrea Bonetti.) A. Bonetti and A. Burg are with the Telecommunications Circuits Labora- tory (TCL), École Polytechnique Fédérale de Lausanne (EPFL), 1015 Lau- sanne, Switzerland (e-mail: andrea.bonetti@epfl.ch; andreas.burg@epfl.ch). R. Golman, R. Giterman, and A. Teman are with the Faculty of Engineering, Bar-Ilan University, Ramat Gan 5290002, Israel (e-mail: roman.golman@biu.ac.il; robert.giterman@biu.ac.il; adam.teman@biu.ac.il). Color versions of one or more of the figures in this article are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TVLSI.2019.2955933 (SRAM) is used. Dynamic random access memory (DRAM) offers a significant advantage over SRAM for large memory sizes, as it provides higher memory density by using only a one-transistor one-capacitor (1T-1C) storage cell. Furthermore, even though DRAMs need a periodic refresh to avoid loss of data, their leakage power is highly reduced as compared with that of SRAMs due to the absence of direct leakage paths between the supply voltage and ground. Among the different DRAM topologies, gain-cell embed- ded DRAM (GC-eDRAM) [5] is a fully logic-compatible embedded memory that does not require any dedicated process steps during manufacturing. Given both its high-density and low-latency operations, GC-eDRAM has proven to be a valid and low-power alternative to SRAM [6]–[11]. Access- ing GC-eDRAMs are faster than conventional 1T-1C-based DRAMs, as active elements are used to implement the read port of the gain cell (GC), which is the fundamental storage unit. Moreover, dual-port operation is inherently provided by GC-eDRAMs, as GCs include separate write and read ports. Finally, as opposed to conventional DRAMs, the read is nondestructive in GC-eDRAMs; therefore, the overhead of writing back the data after read is avoided. The design space of memories is highly complex due to the presence of a large number of design variables, which have significant effects on the memory performance metrics. For this reason, high-level modeling tools for embedded memories are key for a fast exploration of this design space to facilitate the choice between several design options without the need for many long and complex full design iterations that also include many several time-consuming transient SPICE simu- lations. Thus, sufficiently accurate high-level models change the design space exploration from a manual work of hours to an automated process of seconds. In fact, such modeling tools find applications in two main areas. 1) Memory Design: Modeling tools can assist designers by predicting the performance impact of important design choices early in the development cycle during the pre- liminary stage of the design phase. 2) System Architecture: Architectural optimization and design-space exploration of complex SoCs heavily rely on accurate performance estimation of their embedded memories. For this reason, high-level memory design and integration of memory modeling tools with system simulators [12] is an integral part of the system development. A number of modeling tools for conventional DRAMs have already been proposed in the literature [12]–[15]. Even though each of these tools provides a certain degree of flexibility, none of them can be adapted to reflect the behavior of GC-eDRAM. 1063-8210 © 2020 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.