Indian Journal of Science and Technology, Vol 9(47), DOI: 10.17485/ijst/2016/v9i47/108453, December 2016 ISSN (Print) : 0974-6846 ISSN (Online) : 0974-5645 * Author for correspondence 1. Introduction Filter designs are the most concentrated design among all the DSP blocks available. Te reason behind this is being the signals cannot travel without the interference of noise signals from any kind of transmitter or receiver. Te disturbance observed or corruption caused during the communication of any type of wanted signal is defned as a noise signal. Because signals are being surrounded by the variety of interferences. Few examples to illustrate are, delay in the signals and overlapping of too many signals 1 . Any area of technology like speech processing, heavy machinery, high magnetic radiation devices echo cancellation, Interferences of noise signals have taken a huge growth. Te main diference that makes in designing an adaptive flter rather than using a fxed co-efcient adaptive flter is, the adaptive LMS flter continuously monitors the level of noise to signal levels 2 and adaptively eliminates from the desired signal to make the error factor almost zero. Tis process is carried out by adaptive updating or changing the value of co-efcient used adaptive flters. To aid this vast advantage of adaptive flters, we present a method to increase the overall performance of the flter by hardware- sofware co-design which does not change any design or the parameters of the original architecture. Te design and implementation of adaptive flters are created in Simulink, the entire architecture is profled to examine the portion of the code that consumes most of its time in execution. Te portion of the code consuming maximum execution is separately Abstract Objectives: A hardware-software co-design of Least Mean Square (LMS) adaptive FIR filter utilized for the real time noise cancellation purpose has been designed and demonstrated. Method/Analysis: This LMS adaptive filter which serves as a better choice in filtering real-time signals with noise, is being designed as an IP for various different users to make the filter reconfigurable to their designs. Fascinating feature about creating an IP on Zedboard which belong to the Zynq series of FPGA boards is to design the LMS filter in Simulink and convert to RTL (Register Transfer Level) logic by employing HDL coder. This process simplifies the task of either writing an HDL code or designing circuits using transistors, which is time-consuming and cumbersome. Findings: To estimate the performance the IP designed is profiled with the Simulink of MATLAB to estimate the functions, which takes more time for execution in the Simulink design of LMS adaptive filter. Profiling the application, it has been found out that LMS algorithm block for the calculation of adaptive coefficients takes around 311.63ns time/call of the execution time. Hence only this block is imported to FPGA as a soft-core block and interconnected with the hardcore ARM cortex A9 processor block which achieves hardware-software co-design of LMS adaptive filter. Application: This method simplifies the process of hardware-software co-design process, which can be applied to any complex design that can be generated from MATLAB/Simulink and generate the same design as an application to run on an advanced FPGA board. Keywords: Field Programmable Gate Array (FPGA), IP (Intellectual Property), LMS (Least Mean Square) Algorithm, Simulink, ZedBoard (Zynq Evaluation and Development Board) Development of Adaptive LMS Filter IP on Zedboard for Hardware-software Co-design V. Jean Shilpa 1* , P. K. Jawahar 1 and S. Karthik 2 1 Department of ECE, B.S. Abdur Rahman University, Chennai - 600048, Tamil Nadu, India; Jeanshilpa@bsauniv.ac.in, jawahar@bsauniv.ac.in 2 Department of ECE, SRM University, India; skarthikvit@gmail.com