Characterization of Oxide Defects in InGaAs MOS Gate Stacks for High-Mobility n-Channel MOSFETs (Invited) J. Franco * , V. Putcha 1 , A. Vais, S. Sioncke, N. Waldron, D. Zhou, G. Rzepa 2 , Ph. J. Roussel, G. Groeseneken 1 , M. Heyns 1 , N. Collaert, D. Linten, T. Grasser 2 , B. Kaczer imec, Leuven – Belgium, 1 also at KU Leuven – Belgium , 2 TU Wien – Austria * Jacopo.Franco@imec.be Abstract—We review our recent studies of oxide traps in InGaAs MOS gate stacks for novel high-mobility n-channel MOSFETs. We discuss and correlate various trap characterization techniques such as Bias Temperature Instability, defect Capture-Emission-Time maps (applied here to InGaAs devices), Random Telegraph Noise, hysteresis traces, multi-frequency C-V dispersion, all performed on a variety of device test vehicles (capacitors, planar MOSFETs, finFETs, nanowires). Finally we demonstrate guidelines for developing sufficiently reliable IIIV gate stacks. Introduction High-mobility channel materials are considered for future CMOS nodes, as they can offer enhanced device performance at reduced voltage [1], and therefore reduced active power dissipation. For n- channel devices, IIIV materials offer a dramatic boost of electron mobility [2]. In particular, InGaAs also enables bandgap engineering by varying the In-to-Ga ratio. We have recently demonstrated In0.53Ga0.47As devices in advanced VLSI-compatible architectures with performance almost on par with state-of-the-art Si devices but at a remarkably lower operating voltage (Fig. 1) [3- 7]. Most commonly, Al2O3-based gate stacks are used on InGaAs, due to a surface self-cleaning effect of the relative ALD process [8]. An excessive interaction of carriers with oxide defects represents a crucial challenge for IIIV devices [9-11]. Various symptoms are observed in the device electrical characteristics (Fig. 2), e.g., frequency-dispersion of the capacitance-voltage (C-V) curve in strong accumulation [12]; instability of the device threshold voltage (Vth), subthreshold swing (SS), and transconductance (gm) [9]; hysteresis in double-sweep C-V or ID-VG traces [13]; Random Telegraph Noise inducing abrupt jumps in nanoscale device I-V’s [14]. While oxide defects are also observed and studied in Si devices [15], their impact is exacerbated in IIIV devices due to defective semiconductor-oxide interfaces, unsuitability of the semiconductor native oxides as interfacial layers [16], and process thermal-budget limitations affecting the quality of the high-k layers [17]. We first review the understanding of charge trapping in oxide defects based on Si literature. We then discuss Positive Bias Temperature Instability (PBTI) measurements in InGaAs devices, and compare the results with Si. We show that the PBTI signatures are common across all device architectures, while scaling introduces additional challenges such as quantization effects, Random Telegraph Noise and variability. We discuss the distribution of defect energy barriers, which dictates the charge trapping transients in Al2O3-based InGaAs gate stacks. We then discuss alternative characterization techniques, such as multi-frequency C-V dispersion and hysteresis, and correlate them to BTI. Finally we discuss our recent demonstrations of reliable gate stacks for InGaAs devices. Charge Trapping in Oxide Defects Based on the Si literature, the understanding of charge trapping in oxide defects can be summarized as follows (Fig. 3): distributions of allowed energy levels exist within the dielectric bandgap, originating from microscopic defects (e.g., hydroxyl E’-center in SiO2, oxygen vacancies in high-k oxides). Depending on the position of the channel Fermi level, a fraction of these defects can (de-)trap carriers. Energy barriers are involved in the charge exchange process, related to the reconfiguration of the atomic bonds at the defect site, resulting in trapping being strongly temperature activated [τc ∝ exp(Ec/kT), τe ∝ exp(Ee/kT)]. The process can be approx. represented as a two-parabolic-well system with distributed curvatures representing the spread of energy barriers within a population of defects in an amorphous oxide [15,18]. The behavior of an ensemble of defects can be described with a bi-variate Normal distribution of capture and emission energy barriers, which can be converted into the Capture-Emission-Time (CET) map observable at a given operating temperature [19,20,21]. This methodology is applied here for the first time to a typ. Al2O3-based InGaAs gate stack to project the device aging during operation in a digital circuit. Positive Bias Temperature Instability Fig. 4 reports typical PBTI measurements on an InGaAs MOSFET with a 10nm Al2O3 gate dielectric. A sequence of stress phases (VG=Vstress) of increasing durations, alternated with sense phases (VG=Vth0 for a MOSFET, or =Vfb0 for a MOS capacitor) is applied to the device to estimate the ΔVth (or ΔVfb) induced by charge trapping. The measurement is repeated on multiple pristine devices using increasing stress voltage overdrives, as increasing oxide electric field (Eox) allows channel carriers to interact with a wider range of defect levels (cf. Fig. 3a). The ΔVth follows a power-law- like kinetics with time exponent n~0.1 (typ. Si: ~0.16), and similarly a power-law-like dependence of the stress overdrive, with exponent γ~1.5 (typ. Si: 6~7). The measured data can be used to estimate for each stress voltage the time-to-failure, i.e., the time necessary to reach a failure criterion defined as ΔVth=30mV, and consequently to determine the maximum operating voltage for 10 year reliability. With BTI being accelerated by Eox, it is convenient to define a benchmark which takes into account the oxide thickness when comparing different gate stacks. The ΔVth measured after a fixed stress time (e.g., 1s) can be converted into an equivalent charge sheet density ΔNeff=ΔVth*Cox/q, and plotted vs. the applied equivalent Eox=Vov/CET (Fig. 5). Data of Al2O3-based InGaAs gate stacks with various oxide thicknesses (EOT: 5~1.4nm) line up in such a plot. In order to meet a standard BTI reliability target of ΔVth=30mV after 10 years, acceptable ΔNeff values should be in the low 10 10 cm -2 range (assuming a target EOT of 1nm and a power-law time exponent n of 0.1~0.16) or below, consistent with Si data. In contrast, InGaAs devices show ~10× larger ΔNeff. The ΔNeff plot also preserves the crucial information about the BTI voltage acceleration exponent: significantly lower γ values are observed in InGaAs gate stacks as compared to Si. This is ascribed to a wide distribution of oxide defect levels at energies close to the channel Fermi level: defects are accessible already at low Eox, and therefore the device reliability is jeopardized irrespective of the operating VDD (cf. Eox~2MV/cm vs. ~3.5MV/cm marked as Low Power, ‘LP’, vs. High Performance, ‘HP’, in Fig. 5a). On the contrary, a narrow distribution of defect levels decoupled from the channel Fermi level results in a higher γ, as channel carriers can get trapped only at high Eox (Fig. 5b). A. Impact of the device architecture The ΔNeff measured at a given Eox (e.g., 3.5MV/cm) is an indicator of the accessible defect density in an oxide. Similar ΔNeff values are measured on various device test vehicles (from simple MOS capacitors, to finFETs, nanowires, and even tunnel-FETs despite their SS being insensitive to oxide traps [22]), irrespective of the oxide thickness and of the actual dielectric composition (Al2O3- 978-1-5386-3559-9/17/$31.00 ©2017 IEEE 7.5.1 IEDM17-175