Digital Phase-Locked Loop and its Realization Tsai-Sheng Kao 1 , Sheng-Chih Chen 2 , Yuan-Chang Chang 1 , Sheng-Yun Hou 1 , and Chang-Jung Juan 1 1 Department of Electronic Engineering, Hwa-Hsia Institute of Technology. No. 111 Gong Jhuan Road, Chung Ho, Taipei County 23568, Taiwan, R.O.C. TsaiShengKao@gmail.com 2 Graduate Program of Digital Contens and Technologies, ChengChi University. No. 64, Sec. 2, ZhiNan Rd., Wenshan District, Taipei City 11605, Taiwan, R.O.C. Abstract: The realization of a digital phase-locked loop (DPLL) requires to choose a suitable phase detector and to design an appropriate loop filter; these tasks are commonly nontrivial in most applications. In this paper, the DPLL system is first formulated as a state estimation problem; then an extended Kalman filter (EKF) is applied to realize this DPLL for estimating the sampling phase. Therefore, the phase detector and loop filter are simply realized by the EKF. The proposed DPLL has a simple structure and low realization complexity. Computer simulations for a conventional DPLL system are given to compare with those for the proposed timing recovery system. Simulation results indicate that the proposed realization can estimate the input phase rapidly without causing a large jittering. Key–Words: Digital phase-locked loop (DPLL), state estimation, extended Kalman filter (EKF) 1 Introduction Phase-locked loop (PLL) which constitutes a basic building block for many synchronizers like carrier re- covery or timing recovery is essential in most digi- tal communication systems. Owing to the continued advancement in VLSI, all digital phase-locked loop (DPLL) has been under extensive investigation for several years [1, 2]. To realize a DPLL system, how- ever, the selection of a phase detector [3, 4, 5] is cru- cial and the design of a loop filter is nontrivial. A DPLL is, in general, a nonlinear system due to the nonlinear behavior of the phase detector. Unfortu- nately, few studies have been published on modeling a phase detector. Hence, the loop filter design often ig- nores the dynamics of the phase detector, causing the performance of the DPLL less reliable. The conven- tional loop filter design involves in selecting the order of the loop filter and determining its loop gains such that the performance of a DPLL satisfies fast phase acquisition and small phase jitter. However, the two characteristics of conventional DPLL systems with fixed loop gains are contradictory since fast phase acquisition requires wide loop bandwidth and small phase jitter requires narrow loop bandwidth [6, 7]. Moreover, the determination of the loop gains is dif- ficult using the transfer function approach, especially when the order of the loop filter is high. A Kalman fil- ter (KF) was realized as a loop filter to fulfill the above characteristics together with time-variant loop gains [8, 9, 10, 11], and these Kalman gains were shown to be equivalent to the time-variant loop gains of a DPLL. The performance of this DPLL bit synchro- nizer is significantly improved by using these time- variant loop gains in place of the fixed gains of a con- ventional DPLL. Although Driessen [8] used a KF to realize the loop filter of a DPLL, this realization did not take the phase detector into account and the timing informa- tion was assumed to be known in advance. In this pa- per, we use an extended Kalman filter (EKF) to realize the loop filter as well as the phase detector of a DPLL, and the loop gains are easily obtained via the extended Kalman filtering techniques. The proposed system has a simple structure and low realization complexity. The rest of the paper is organized as follows. In section II, the channel model is described and the function of a DPLL is briefly reviewed. In section III, we formulate the DPLL system as a state estima- tion problem and apply an EKF to realize this DPLL. In section IV, phase domain models of both a conven- tional DPLL and the proposed EKF-based DPLL are described. In section V, simulations are shown to ver- ify the proposed DPLL. Finally, conclusions are given in section V. Proceedings of the 9th WSEAS International Conference on APPLIED INFORMATICS AND COMMUNICATIONS (AIC '09) ISSN: 1790-5109 415 ISBN: 978-960-474-107-6