580 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 14, NO. 3, MAY2015 Quantum Well InAs/AlSb/GaSb Vertical Tunnel FET With HSQ Mechanical Support Yuping Zeng, Chien-I Kuo, Chingyi Hsu, Mohammad Najmzadeh, Member, IEEE, Angada Sachid, Rehan Kapadia, Chunwing Yeung, Edward Chang, Chenming Hu, Fellow, IEEE, and Ali Javey Abstract—A type-III (broken gap) band alignment heterojunc- tion vertical in-line InAs/AlSb/GaSb tunnel FET, including a 2-nm- thin AlSb tunneling barrier is demonstrated. The impact of overlap and underlap gate is studied experimentally and supported further by quasi-stationary 2-D TCAD Sentaurus device simulations. Hy- drogen silsesquioxane is used as a novel mechanical support struc- ture to suspend the 10-nm-thin InAs drain with enough undercut to be able to demonstrate an overlap gate architecture. The over- lap gate InAs/AlSb/GaSb TFET shows an ON current density of 22 μA/μm 2 at V GS = V DS =0.4 V and the subthreshold slope is 194 mV/decade at room temperature and 46 mV/decade at 100 K. Index Terms—Heterojunction, nanofabrication, TCAD simula- tion, tunneling barrier, type III (broken gap) band alignment, ver- tical in-line tunnel FET. I. INTRODUCTION T UNNEL field effect transistors (TFETs) have been exten- sively explored for their potential as promising candidates for ultra-low power, low voltage nanoelectronic applications [1]–[13]. III–V materials, due to their small effective masses, promise a high tunneling probability and therefore, a high ON current [14]. In addition, the large variety of band alignments offered by III–V materials provides an opportunity to design a heterojunction with a small energy offset between the valence band on one side of the junction and the conduction band on the other side of the junction [15]. The overlap of the two bands, and thus the ON current of the transistor can be tuned by applying a voltage to a nearby gate electrode. InAs/GaSb is one material system that offers a type III (broken gap) band alignment and can provide high ON current TFETs [16]. A previous simulation work on III–V vertical in-line TFETs has highlighted the impact of the drain (InGaAs) layer thickness in the undercut access region [17] and the device geometrical Manuscript received October 19, 2014; accepted March 29, 2015. Date of publication April 7, 2015; date of current version May 6, 2015. This work was supported by the E3S National Science Foundation Award EECS-0939514. The work of M. Najmzadeh and A. Sachid was supported by ATMI, Inc., and Applied Materials, Inc., under the iRICE Program. The review of this paper was arranged by Associate Editor E. Tutuc. Y. Zeng, M. Najmzadeh, A. Sachid, R. Kapadia, C. Yeung, C. Hu, and A. Javey are with the Electrical Engineering and Computer Science Department, University of California, Berkeley, CA 94720 USA (e-mail: yupingzeng@eecs. berkeley.edu; ajmzadeh@eecs.berkeley.edu; angada@berkeley.edu; kapadia. rehan@gmail.com; tallwing@gmail.com; hu@eecs.berkeley.edu; ajavey@ eecs.berkeley.edu). C.-I Kuo, C. Hsu, and E. Chang are with the National Chiaotung Univer- sity, Hsinchu 300, Taiwan (e-mail: cikuo@faculty.nctu.edu.tw; captainap0220@ gmail.com; edc@mail.nctu.edu.tw). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TNANO.2015.2419232 design, including the gate length and gate undercut [11], [18]. For this general device architecture, the most promising config- uration to operate in ultra-low voltage regime, and to be able to obtain a high ON current, is a type III band alignment. The III–V vertical TFETs with this configuration reported in the literature [8], [9], [17]–[19] do not have an ultra-thin tunneling barrier. As a result, the conduction and valence band edges at the tunneling junction are pinned, resulting in a fixed band offset that cannot be modulated by the gate. In this paper, we report a platform to fabricate an overlap gate InAs/AlSb/GaSb vertical in-line TFET. This is the first III–V broken gap band alignment heterojunction TFET with a 2 nm thin AlSb tunneling barrier. HSQ layer was used to support a thin InAs layer together with the drain electrode of the tunnel FET. Without the HSQ layer, the InAs layer would bend or collapse during further processing. II. NANOFABRICATION OF OVERLAP AND UNDERLAP QUANTUM WELL INAS/ALSB/GASB VERTICAL TFETS A. The InAs/AlSb/GaSb Epitaxial Substrate Platform for a Type III Band Alignment Fig. 1 depicts the device fabrication process. The initial 50 mm epitaxial substrate wafer includes 10 nm thin n-type InAs layer (Si doped), 2 nm un-doped AlSb layer, 3 nm un- doped GaSb layer and 50 nm p + GaSb layer (C doped, 1 × 10 19 cm −3 ). Two n-type doping levels of 1 × 10 17 and 5 × 10 18 cm −3 were explored for the InAs layer. The 2 nm thin AlSb, a sandwiched tunneling barrier between the InAs and GaSb layers, would allow the InAs conduction band (ground quantum well energy state) to slide easily up and down in energy relative to the valence band of GaSb and therefore, leading to modulation of electron tunneling under the control of an applied gate voltage. Without the AlSb layer, the energy bands of InAs and GaSb would be fixed relative to their Fermi levels. The 10 nm thin InAs layer is confined between the gate oxide layer and the AlSb layer, forming a quantum well. The 200 nm heavily doped GaSb layer (7 × 10 19 cm −3 ) is designed to be thick enough for the aggressive drain mesa etching. The remaining non-etched GaSb layer serves as the source contact layer. The 90 periods of AlAs/AsSb supperlattice buffer layer functions as the isolation foundation for the devices. B. Nanofabrication of Overlap and Underlap Gate Devices MAA/PMMA bilayer resist stack was spin coated and elec- tron beam lithography was used to form T-shape troughs in the resist, exposing the InAs at the bottom of each trough. 10 nm 1536-125X © 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications standards/publications/rights/index.html for more information.