International Journal of Innovative Technology and Exploring Engineering (IJITEE) ISSN: 2278-3075, Volume-8 Issue-10, August 2019 852 Published By: Blue Eyes Intelligence Engineering & Sciences Publication Retrieval Number J90400881019/2019©BEIESP DOI: 10.35940/ijitee.J9040.0881019 Abstract: Recently, low-power consuming devices are gaining demand due to excessive use and requirement of hand-held & portable electronic gadgets. The quest for designing better options to lower the power consumption of a device is in high-swing. The paper proposes two 32 x 32 – bit multipliers. The first design is based only on the Urdhava Tiryakbhyam Sutra of Vedic Mathematics. The use of this sutra has created a multiplier with higher throughput and lesser power utilization than conventional 32 x 32 – bit multipliers. The second design incorporates the reversible logic into the first design, which further reduces the power consumption of the system. Thus bringing together Vedic sutra for multiplication and reversible gates has led to the development of a Reversible Vedic Multiplier which has both the advantages of high-speed and low-power consumption. Index Terms: FPGA, High speed, Low power, Reversible Gates, Urdhava Tiryakbhyam Sutra, Vedic Multiplier. I. INTRODUCTION Low power usage is a major requisite in electronic systems. The demand of such systems is inversely proportional to its power consumption. Increased throughput of the system is an added advantage and the market is in need for such systems. Multiplication is an unavoidable process for systems dealing in signal processing, acoustics, communication and wireless technology [1]. The greater the bit size of the input to the multiplier, the greater the delay in receiving the output. Many research works have been focused on reducing the power requirement and decreasing the delay in generating outputs of a multiplier [2]. To develop a system with greater speed and lower power consumption, it is thus required to optimize the multipliers [3]. It has been understood that Vedic multipliers produce faster response than standard multipliers. Also use of Reversible logic gates limits the use of power. These two techniques are employed together to design two 32 x 32 – bit multipliers, both of which consume low power and provide quick outputs. Vedic Mathematics, is well-known for its simplicity and mental calculation capability [4]. It is a collection of 16 different formulae, applicable to all areas of mathematics like arithmetic, geometry, calculus, algebra, trigonometry and conics [3], [5]. The Urdhava Tiryakbhyam (UT) sutra is the only formula in Vedic Mathematics, out of the 16, which is applicable for all general types of multiplication [6]. The use of this sutra allows parallel generation of partial products (PP) during multiplication. The Revised Manuscript Received on August 05, 2019 Ansiya Eshack, Department of Electronics, School of Technology and Applied Sciences, Edapally, Ernakulam 682024 S. Krishnakumar, Department of Electronics, School of Technology and Applied Sciences, Edapally, Ernakulam 682024 final output is got faster due to this process and thus greatly improves the speed of the system [7]. Reversible logic is a key area attracting a lot of research in the past decades [8]. Circuits employing reversible gates are low power-consuming as they do not lose information during the logic implementation. A reversible gate is represented by ‘n * n’ which indicates it has ‘n’ inputs and ‘n’ outputs. There is a one to one mapping between the inputs and outputs of a reversible gate [9], [10]. Most notable reversible gates are Fredkin, Toffoli and Peres [11]. The paper presents two designs of 32 x 32 – bit multiplier. The first design applies the UT Sutra for performing the multiplication. Results show this design utilizes less power and has high speed. The second design makes use of Reversible logic gates along with the UT sutra. It employs 3 * 3 Toffoli gates for the logic execution. It is observed that this multiplier consumes lower power than the 1 st design. The rest of the paper is as follows: Section II deals with Vedic mathematics and the UT sutra. The reversible gates are described in Section III. The design and implementation of the two 32 x 32 – bit multipliers are explained in Section IV. Results and discussion are provided in Section V, and conclusion in Section VI. II. VEDIC MATHEMATICS AND UT SUTRA Vedic Mathematics is the contribution of Shri Bharati Krishna Tirthaji Maharaja and is based on the Vedas [3]. It contains sutras (formulae) which help solve mathematical problems a lot easier and faster than the conventional system of mathematics. His findings were published in a book called Vedic Mathematics. It has been observed that use of Vedic Mathematics to solve problems reduces the time taken for calculation, when compared with regular mathematics [6]. The advantage of this is the use of mental calculations and little or no use of pen and paper to reach the results. The UT sutra is one of the 16 sutras in Vedic mathematics. This sutra meaning “Vertical and Crosswise” follows vertical and crosswise multiplication between the bits of the input [12]. It follows a pattern which can be represented by a line diagram. The line diagram of a multiplier having two 2 – bit inputs, 4 – bit inputs and 8 – bit inputs are shown in Fig. 1(a), (b) and (c). Low Power 32 x 32 – bit Reversible Vedic Multiplier Ansiya Eshack, S. Krishnakumar