A 2.4GHz IEEE 802.15.6 Compliant 1.52nJ/bit TX & 1.32nJ/bit RX Multiband Transceiver for Low Power Standards Mustafijur Rahman Radio Circuits & Technology Lab Intel Labs, Hillsboro, USA mustafijur.rahman@intel.com Ramesh Harjani Dept. of Electrical & Computer Engineering University of Minnesota, Minneapolis, USA harjani@umn.edu Abstract—This paper describes an 802.15.6 compliant 2.36- 2.484GHz multiband transceiver that uses an energy efficient programmable digital power amplifier on the transit side and a zero power passive voltage gain frontend using a 1:3 balun on the receive side to achieve low power operation. A 7 th harmonic injection locked oscillator and zero power passive polyphase filter generates the phases at 2.4GHz required for phase modulation on the transmit side and for LO generation on the receive side. This enables channel selection using a 342.86 MHz PLL, i.e., at 1/7th of the RF frequency of 2.4GHz to result in low power consumption. The prototype transmitter consumes 1.48 mW of power while delivering -9.47dBm output power resulting in an energy efficiency of 1.52nJ/bit at 971kbps data rate. The measured RMS EVM for π/4 DQPSK modulation is 5.68%. The prototype receiver consumes 1.29mW of power resulting in an energy efficiency of 1.32nJ/bit while achieving a receiver noise figure of 10.2dB and an IIP3 of -24.1 dBm. This design does not use offchip inductors. I. I NTRODUCTION Due to the large expected number of connections in 5G and the advent of IoT and WBAN there is an increased demand for low power radios [1]–[3]. Unfortunately, traditional radio transmitters based on homodyne or super-heterodyne conver- sion schemes are power hungry due to the presence of phase locked loops (PLLs) operating at the RF frequency, need for linear mixers and high performance data converters. Further, transmitters based on polar modulation lead to more complex circuit designs. On the receive side, traditional architectures turns out to be power hungry due to the presence of the LNA at RF, linear mixers and high performance ADCs. In this paper we present a transceiver compatible with the IEEE 802.15.6 standard [4] which employs 7 th harmonic injection locking to generate phases at RF thereby drastically reducing power. The transmitter uses an energy efficient fully programmable digital power amplifier with pulse shaping capability. The receiver has a zero IF architecture and uses zero power passive voltage gain and passive voltage mode mixers to substantially reduce power consumption. II. BLOCK DIAGRAM The block diagram of the complete transceiver is shown in Fig. 1. The transmitter consists of a digital phase-MUX based PA which uses sinusoidal quadrature phases for PSK modulation. The sinusoidal quadrature phases are generated by a passive polyphase filter driven by an oscillator at 2.4GHz which is injection locked to the 7 th harmonic of the reference at 342.86MHz. A pulse slimmer [5] enhances the 7 th harmonic Digital PA DIGITAL BASEBAND (FPGA) Reference @RF/7 Slimmer BB Amp 2.4 GHz 7X Digital Pulse Shaping POLYPHASE FILTER 7X X 4 I/Q Zero power Zero IF Fig. 1. Block diagram for the proposed low power transceiver content at 2.4 GHz. Consequently, channel selection can be achieved by an integer N PLL running at 1/7 th the RF frequency which drastically reduces power consumption for frequency synthesis. In this prototype design the standard integer-N PLL needed has not been included. However, its impact on the overall architecture and power consumption has been discussed in the measurements section of the paper. The receiver is based on a zero IF I/Q architecture. It employs a passive gain stage followed by passive mixers and class AB baseband amplifiers for demodulation of the received signal. III. CIRCUIT DIAGRAM The circuit diagram for the transmitter is shown in Fig. 2. A 342.86 MHz external reference at 1/7 th RF frequency is applied to a pulse slimmer. The slimmer generates pseudo differential outputs suitable for injection locking. It consists of a duty cycle control stage to enhance the 7 th harmonic followed by a differentiator which suppresses lower harmonics and eliminates even order harmonics [5]. The ILO is a PMOS- NMOS current reuse oscillator which is followed by a low power LC tuned buffer. The cross-coupled pair transistors are low threshold (Vt) devices so that they contribute maximum gm for the same overdrive voltage. However, the tail current source transistor is a high threshold (Vt) device to prevent leakage due to the low threshold (Vt) devices in the cross- coupled pair. The LC buffer drives a zero power passive RC polyphase filter and generates sinusoidal quadrature I/Q phases. The quadrature phases are again buffered by a drive amplifier (DA)/LO buffer which distributes the signal to the digital power amplifier on the TX side as well as to the mixers on the RX side to serve as the LO. The transmitter consists of a digital phase-MUX based power amplifier which uses the sinusoidal quadrature phases to 821 978-1-5386-9562-3/18/$31.00 ©2018 IEEE