734 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 6, JUNE 1999 MOSFET-Only Switched-Capacitor Circuits in Digital CMOS Technology Hirokazu Yoshizawa, Yunteng Huang, Paul F. Ferguson, Jr., and Gabor C. Temes, Life Fellow, IEEE Abstract—Design techniques are described for the realization of precision high-linearity switched-capacitor (SC) stages con- structed entirely from MOS transistors. The proposed circuits use the gate-to-channel capacitance of MOSFET’s for realizing all capacitors. As a result, they can be fabricated in any inexpensive basic digital CMOS technology, and the chip area occupied by the capacitors can be reduced. A number of different SC stages have been designed and fabricated using the proposed techniques. These included SC am- plifiers, gain/loss stages, and data converters. Both the simulations and the experimental results obtained indicate that very high linearity (comparable to that achieved using analog fabrication processes with two poly-Si layers) can be achieved in these circuits using basic CMOS technology. Index Terms— Delta–sigma modulators, MOSFET capacitors, operational amplifiers, programmable gain amplifiers, switched- capacitor amplifiers, switched-capacitor circuits. I. INTRODUCTION I N mixed-mode (combined analog-digital) CMOS IC’s, the digital circuitry usually requires only a single poly-Si layer for the gates. However, for linear operation, the analog stages generally require high-linearity capacitors, which are normally realized between two poly-Si (“poly”) layers, adding a second poly layer for this purpose. This increases the cost of fabrication significantly. Using poly-metal, metal-metal, or special poly-metal-metal sandwich construction, the second poly layer can be avoided, but the thick oxide used in these structures requires a large chip area per unit capacitance and yields a large parasitic capacitance to the substrate. Recently, there have been several attempts to use the gate- to-channel capacitance of MOSFET’s as the capacitors needed in analog CMOS circuits [1]–[6]. There are several advantages in doing this: such capacitors (to be called “MOSCAP’s” in this paper) are always available in any MOS process. Also, due to the thin oxide used, they provide a large capacitance per unit area—several times (e.g., for the Orbit 1.2- m process, three times) that of a poly-poly capacitor and 20–30 times that of Manuscript received December 19, 1997; revised January 12, 1999. The work of H. Yoshizawa was supported by Seiko Instruments, Inc. The work of Y. Huang and G. Temes was supported by the National Science Foundation Center for the Design of Analog/Digital Integrated Circuits under Grant INT- 9633040 and by Analog Devices, Inc. H. Yoshizawa was with Oregon State University, Corvallis, OR 97331 USA. He is now with Seiko I Asic Co., Ltd., Chiba 270-2222 Japan. Y. Huang was with Oregon State University, Corvallis, OR 97331 USA. He is now with Silicon Laboratories, Inc., Austin, TX 78735 USA. P. F. Ferguson, Jr., is with Analog Devices, Inc., Wilmington, MA 01887 USA. G. C. Temes is with Oregon State University, Corvallis, OR 97331 USA. Publisher Item Identifier S 0018-9200(99)04199-2. a poly-metal or metal-metal one. (Using a poly-metal-metal sandwich capacitor instead of a poly-metal or metal-metal one will yield a larger capacitance per unit area. However, in some processes, such a sandwich capacitor is not recommended because the formation of hillocks can penetrate the dielectric layer and cause shorts [7].) In addition, thanks to the smoother surface of the crystalline Si, the random capacitance variation due to poly granularity is reduced, and the matching accuracy is hence improved compared to other realizations [7], [8]. Last, the ratio between the parasitic capacitance to the substrate and the main capacitance realized is usually smaller than for other structures [9]. On the other hand, compared to poly-poly implementations, additional space between the MOSCAP’s is required to ac- commodate the design rule on well-to-well spacing, and the MOSCAP matching precision is slightly lower due to edge effects produced by MOS device processing. The main disadvantage of the MOSCAP device is the large voltage dependence of the capacitance realized. Unless highly doped regions are diffused under the gate (which requires an additional mask and additional processing steps in self-aligned digital CMOS technologies), the gate-to-channel capacitance will vary greatly in all regions of operation (strong inversion, depletion, or accumulation) with the voltage across it. Even when a MOSCAP is biased deeply in the accumulation region (with 2 V or more gate-to-channel dc bias voltage), the voltage coefficient is usually at least 800 ppm/V, and it can be many times higher. Previous work [1], [2] indicated that this nonlinear effect limits the ratio of signal (S) to total harmonic distortion (THD) to around 60 dB, a value that is inadequate for many important applications (data converters, audio, etc.) of analog CMOS IC’s. There are several ways of creating a MOSFET-based ca- pacitor [1]. The device may be in a well or in the substrate; also, the channel may be created by accumulation or by strong inversion. To realize floating capacitors, the well-embedded device was chosen in this work. Also, we opted for using accumulated channels, in part to reduce the bias voltage needed to keep the device in a reasonably linear operational range and in part to minimize the frequency dependence of the gate-channel capacitance. In Section II, the effects of capacitor nonlinearity on the operation of switched-capacitor (SC) circuits will be analyzed. It will be shown that only the nonlinearities of the input and output branches affect the overall THD of the system. Section III describes simple compensation techniques for these branches: by combining two or more nonlinear capacitors 0018–9200/99$10.00  1999 IEEE