40 Int. J. Communication Networks and Distributed Systems, Vol. 10, No. 1, 2013 Copyright © 2013 Inderscience Enterprises Ltd. A framework for power estimation and reduction in multi-core architectures using basic block approach M. Rajasekhara Babu, P. Venkata Krishna* and M. Khalid School of Computing Science and Engineering, VIT University, Vellore-632015, Tamil Nadu, India E-mail: mrajasekharababu@vit.ac.in E-mail: pvenkatakrishna@vit.ac.in E-mail: mkhalid@vit.ac.in *Corresponding author Abstract: In recent scenarios, power consumption is critical for battery operated devices. There are wide varieties of implementations of dynamic voltage scaling (DVS) algorithm to reduce energy or power. This paper presents a framework called PERMA, power estimator and reducer for multi-core architectures. The PERMA estimates power consumption and suggests analytical procedure to reduce power consumption at basic block level rather than at region level using clock cycles of instructions for a particular architecture (x86). PERMA estimates execution time for each basic block for various voltage levels and chooses best out of these. Therefore, PERMA evaluates the extent to which the voltage can be varied for various Basic Blocks to reduce power consumption without degrading execution time. Finally, it is tested for matrix multiplication of various sizes. There is an improvement in the execution time up to 33.43% with PERMA and 21.89% without PERMA. Keywords: framework; parallelisation; power estimation; power reduction; multi-core. Reference to this paper should be made as follows: Babu, M.R., Krishna, P.V. and Khalid, M. (2013) ‘A framework for power estimation and reduction in multi-core architectures using basic block approach’, Int. J. Communication Networks and Distributed Systems, Vol. 10, No. 1, pp.40–51. Biographical notes: M. Rajasekhara Babu is a senior faculty member at School of Computing Science and Engineering, VIT University, Vellore, India. He completed his Bachelors in Electronics and Communication Engineering from Sri Venkateswara University, Tirupathi, India and took his Masters in Computer Science and Engineering from Regional Engineering College (REC), Calicut, India. Currently, he is pursuing his research at School of Computing Science and Engineering, VIT University, Vellore in the area of multi-core architectures and natural language processing. He has produced number of national and international papers and articles in reputed journals and conferences. His areas of interest include multicore architectures. Also, he is Division Leader of Theoretical Computer Science and Language Translators and Programme Manager for MSc (CS). P. Venkata Krishna is Professor and Division Leader leading a team of about 20 faculty members at the School of Computing Science and Engineering at VIT University, India. He received his BTech in Electronics and