Hindawi Publishing Corporation VLSI Design Volume 2013, Article ID 726324, 9 pages http://dx.doi.org/10.1155/2013/726324 Research Article Low-Power Adiabatic Computing with Improved Quasistatic Energy Recovery Logic Shipra Upadhyay, R. K. Nagaria, and R. A. Mishra Department of Electronics and Communication Engineering, Motilal Nehru National Institute of Technology, Allahabad 211004, India Correspondence should be addressed to Shipra Upadhyay; shipraupadhyay2@gmail.com Received 30 May 2013; Accepted 27 August 2013 Academic Editor: Jose Silva-Martinez Copyright © 2013 Shipra Upadhyay et al. Tis is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Efciency of adiabatic logic circuits is determined by the adiabatic and non-adiabatic losses incurred by them during the charging and recovery operations. Te lesser will be these losses circuit will be more energy efcient. In this paper, a new approach is presented for minimizing power consumption in quasistatic energy recovery logic (QSERL) circuit which involves optimization by removing the nonadiabatic losses completely by replacing the diodes with MOSFETs whose gates are controlled by power clocks. Proposed circuit inherits the advantages of quasistatic ERL (QSERL) family but is with improved power efciency and driving ability. In order to demonstrate workability of the newly developed circuit, a 4 × 4 bit array multiplier circuit has been designed. A mathematical expression to calculate energy dissipation in proposed inverter is developed. Performance of the proposed logic (improved quasistatic energy recovery logic (IQSERL)) is analyzed and compared with CMOS and reported QSERL in their representative inverters and multipliers in VIRTUOSO SPECTRE simulator of Cadence in 0.18 m UMC technology. In our proposed (IQSERL) inverter the power efciency has been improved to almost 20% up to 50 MHz and 300 fF external load capacitance in comparison to CMOS and QSERL circuits. 1. Introduction With increased scaling in CMOS technology, modern designs are capable of performing very high speed computations as the complexity, and the number of devices on a given IC is no longer an issue. Much of the research eforts in the recent decades have been dedicated to improving the speed of dig- ital systems. Tus, high speed computation has become an expected norm for average users. Higher switching activities lead to higher power consumption. Many methodologies have been proposed so far [1] which intended to reduce power consumption, among them adiabatic logic technique [2] is promising alternative. Concept of adiabatic logic circuits is generated from the adiabatic process which is a thermody- namically reversible process that is operated slowly, so that total energy dissipation tends towards zero. Energy dissipated in a circuit depends on how fast the circuit switches or charges and discharges which means that it depends on the approach taken to design the circuit. When the rate of charging will be lower, less amount of energy is drawn from the source. Adia- batic circuits also have another mechanism for energy saving [3] that is based on recovering the energy stored in nodal capacitances. Te quality factor  of any adiabatic process is also known as degree of adiabaticity or adiabatic gain, and it is the ratio between the total energy delivered and the energy that gets dissipated in the whole process. Tere are three types of losses in adiabatic circuits, nona- diabatic losses, adiabatic losses, and leakage losses. Te last two losses are associated with fully adiabatic circuits, whereas nonadiabatic losses are related to quasi/semiadiabatic cir- cuits. Nonadiabatic losses are proportional to the voltage drop across the terminals of a resistive switch, when it is on [4, 5]. Leakage losses are proportional to the clock period and are negligible in comparison to the other two. Te third one is adiabatic loss which depends on current or voltage drawn from the source, load capacitance, charging path resistance, and transition time [6, 7]. It should be noted that nonadiabatic losses can be eliminated completely by using reversible logic, but adiabatic and leakage losses cannot be avoided. Tere are several remedies to reduce adiabatic losses. First one is by extending the charging time . Te second way is constant current charging [8] for capacitance through