Hindawi Publishing Corporation ISRN Electronics Volume 2013, Article ID 673601, 12 pages http://dx.doi.org/10.1155/2013/673601 Research Article DFAL: Diode-Free Adiabatic Logic Circuits Shipra Upadhyay, R. A. Mishra, R. K. Nagaria, and S. P. Singh Department of Electronics and Communication Engineering, Motilal Nehru National Institute of Technology, Allahabad 211004, India Correspondence should be addressed to Shipra Upadhyay; shipraupadhyay2@gmail.com Received 15 November 2012; Accepted 4 December 2012 Academic Editors: S. Nikolaidis and G. Snider Copyright © 2013 Shipra Upadhyay et al. Tis is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Te manufacturing advances in semiconductor processing (continually reducing minimum feature size of transistors, increased complexity and ever increasing number of devices on a given IC) change the design challenges for circuit designers in CMOS technology. Te important challenges are low power high speed computational devices. In this paper a novel low power adiabatic circuit topology is proposed. By removing the diode from the charging and discharging path, higher output amplitude is achieved and also the power dissipation of the diodes is eliminated. A mathematical expression has been developed to explain the energy dissipation in the proposed circuit. Performance of the proposed logic is analyzed and compared with CMOS and reported adiabatic logic styles. Also the layout of proposed inverter circuit has been drawn. Subsequently proposed topology-based various logic gates, combinational and sequential circuits and multiplier circuit are designed and simulated. Te simulations were performed by VIRTUOSO SPECTRE simulator of Cadence in 0.18 m UMC technology. In proposed inverter the energy efciency has been improved to almost 60% up to 100 MHz in comparison to conventional CMOS circuits. Te present research provides low power high speed results up to 100 MHz, and proposal has proven to be used in power aware high-performance VLSI circuitry. 1. Introduction During the past decade, use of adiabatic logic circuits with energy recovery scheme has received considerable attention in high performance low-power applications such as radio- frequency identifcation (RFID) tags, smart cards, and sen- sors because they outperforms in energy efciency without sacrifcing noise immunity and driving ability over their CMOS counterparts. Te power consumption in conven- tional CMOS circuits is proportional to the load capacitance and square of the supply voltage [1, 2], thus researchers have been focused on scaling of the supply voltage and reduc- ing the capacitance to reduce power consumption. For scal- ing the supply voltage the transistor threshold voltage ( t ) must also be scaled down proportionally, however reducing the transistor threshold voltage  t results in proportional increase in subthreshold leakage current. Further the circuit capacitance can be minimized by reducing the sizes of devices but this afects the driving ability of the circuit [3]. Due to the above limitations, in recent years adiabatic sys- tems have been used to reduce power consumption. Various adiabatic logic circuits have been proposed [3–21] working on the energy recovery [4] principle. Te term “adiabatic” is derived from a reversible thermodynamic process [5] and it stands for a system where a transformation takes place in such a way that no gain or loss of heat/energy occurs. Ideally the heat/energy loss can be made almost zero if the transformation takes place sufciently slowly [6]. Te main idea in an adiabatic charging is that transitions are considered to be sufciently slow so that all the nodes are charged or discharged at a constant current. In this way power dissipation is minimized by decreasing the peak current fow [7] through the transistors. Tis is made possible by replacing the DC power source by ramp like power/clock signals [8, 9]. Te energy that is stored in the capacitors during charging is recovered and used in the subsequent computations [10, 11]. It must be noted that systems based on the above mentioned theory of charge recovery are not necessarily reversible. Te