A Novel Parallel Architecture for Low Voltage-Low Power DLL-Based Frequency Multiplier Mohammad Gholami 1 , Mohammad Sharifkhani 2 , Mohsen Hashemi 3 School of Electrical Engineering Sharif University of Technology 1 Mgh_elec@yahoo.com, 2 msharifk@sharif.edu, 3 mohsen.hashemi.ee@gmail.com Abstract— New architecture for a DLL based frequency multiplier for wireless transceivers presents in this paper. This architecture has the advantages of occupy low area, low power, low voltage and low phase noise. DLLs are first ordered systems, so good stability can obtain in this design. This structure also can be used for generating big multiple of reference frequencies. The proposed circuit can operate at a substantially low supply voltage. As an example, the multiplier is adopted to create the 13 times of the reference frequency. The circuit level design is presented. Also power consumption trade-offs are reported. Simulation results confirm the analytical predictions. The proposed DLL-based frequency multiplier is implemented in a 0.13um CMOS Technology. Keywords- Delay locked loop, DLL, Frequency Multiplier, Jitter, Phase noise. I. INTRODUCTION Delay locked loops find wide application in areas such as communication, clock skew, clock recovery circuits [1], wireless systems, frequency multiplier and digital circuits [2], [3], [4]. Frequency synthesizers are used in a large number of communication and instrumentation systems where accurate and stable frequencies are critical. They have gained increased interest, nowadays, mainly in frequency hopping wireless applications where quickly attaining frequency lock is required [5], [6], [7]. When there is no need to multiply the reference frequency, DLLs are used because of their good jitters and phase noise performance and stability [8]. Being first ordered system and always stable, having fast locking time, easier to design and integrate loop filter, all of them are good features of DLLs rather than PLLs [9]. The specific difference between DLLs and PLLs is that, DLLs use VCDL instead of VCO (Fig.1). So in DLLs jitters are only accumulated in one cycle which is not the same as PLLs, in which jitters are accumulated over multiple cycles. Frequency Synthesizers are used to produce a set of frequencies from a single reference source. These frequencies are basically a multiple, either integer or fractional, of the reference frequency. In the case of integer, synthesizers can produce frequencies that are N times the nominal frequency. The use of DLL-based frequency synthesizer is limited because of their unique structure. Fig. 1 shows a simple block diagram of a conventional DLL-based frequency synthesizer. In this structure, only integer and small multiples of the reference frequency can be generated. The main issue in a DLL-based frequency synthesizer is that the edge combiner just can synthesize a fixed and small multiple of the reference ... Fref PD CP Edge Comibner N Delays Fout =N.Fref 1 2 N Vcntl LF Fig. 1. The block diagram of a conventional DLL-based frequency synthesizer Frequency. In this work a new way is shown, which addresses this problem. Parallel of some DLLs are used to generate big multiples of the input frequency. The paper is organized as follows. Next section describes the architecture of the proposed synthesizer. Design guidelines for the circuit and system level implementation of the synthesizer are presented in section III while section IV presents the simulation results. Section V concludes the paper. II. THE PROPOSED ARCHITECTURE FOR DLL-BASED FREQUENCY SYNTHESIZER Fig.1 demonstrates the structure of a DLL-based frequency synthesizer, including VCDL (Voltage Controlled Delay Line), PFD (Phase-Frequency Detector), CP (Charge pump), First order Loop Filter (LF) and Edge Combiner. In a DLL, the input reference clock drives the delay line. The phase of the reference is compared to the phase of the delay line in the PFD. Depending on the time difference between the PFD input signals, a signal at the output of the PFD is generated. The CP provides a proportional charge which is integrated over the loop filter. Therefore, the loop filter’s capacitor gets charged or discharged if there is a time lead or time lag between the reference and the output of the delay line. The capacitor voltage (V cntl ) controls the delay of the delay elements of the delay line. Depending on the phase difference between the input reference clock and output of the last delay, it controls delay of any delay stage, till the two input signals become in-phase. When DLL is in lock, the edge combiner combines the edges of delay stages output’s to get integer multiple of the input frequency. The following equations show the maximum frequency that edge combiner can generate: . out ref f Nf N is Odd  (1) ( / 2). out ref f N f N is Even  (2)