CHARACTERIZATION OF THE SEED SiO 2 LAYER IN STACKED Si0 2 -Ta 2 O 5 GATE DIELECTRICS Pradip K. Roy, Michael A. Laughery and Carlos M. Chacon Bell Laboratories, Lucent Technologies, Orlando, Fl Ayman M. Kanan and Thomas Daugherty Therma-Wave, Inc. Fremont, Ca Abstract A major hurdle in the gate dielectric scaling using conventionally grown Si0 2 has been excessive tunneling that occurs in ultra-thin (<25A) Si0 2 . High dielectric constant materials have high concentrations of bulk fixed charge, unacceptable levels of Si-Ta 2 05 interface trap states, and low Silicon interface carrier mobilities. Stacked Ta 2 0 5 gate dielectrics have alleviated these issues with significant improvements in leakage, tunneling, charge trapping behavior, and interface substructure. Transistors fabricated using this stacked gate dielectric exhibit excellent sub threshold, saturation, and drive currents. In this study, we have characterized the first Si0 2 (8-12A) layer of the Si0 2 - Ta 2 05 stack by ThermaWave (TWI 5240SE) absolute ellipsometry (AE) using He-Ne (X = 630nm) laser light source and by corona oxide semiconductor (COS) non-contact techniques. We have also monitored the kinetics of a thin hydrocarbon layer deposition on top of these films that can be removed by simple heat treatments (250'C - 400'C). Electrical thickness (Tox) of these oxides measured by COS indicates this hydrocarbon layer has no impact on To.. Stacked Ta 2 O5 was synthesized by metal organic chemical vapor deposition (MOCVD) of a 50-75A thick Ta 2 O5 layer at 480'C, 300mTorr followed by an in-situ 550'C UV-0 3 anneal to densify the Ta 2 05 film and grow an additional 5A Si0 2 layer underneath the first grown Si0 2 layer resulting in an effective Si0 2 thickness of 25-30A (process 1). We have done exactly the same deposition schedule after chemically removing the first LP grown Si0 2 layer resulting in an effective SiO 2 thickness of 15-20A (process 2). Transistors are now fabricated for our sub-0.16gm CMOS technologies. These stacked films indicated excellent charge trapping (Dit, Vfb, Qtot), leakage and tunneling characteristics from COS electrical measurements. INTRODUCTION Direct tunneling current increases rapidly when the thickness of Si0 2 gate oxide is reduced below 25A making conventional Si0 2 gate dielectrics not useful for sub-0.1 8pm technologies. According to the 1997 National Technology Roadmap for Semiconductors, the first shipments of 0.151gm-technology based integrated circuits (ICs) will be shipped in 2001. The transistors in these ICs are expected to use gate dielectrics with capacitance equivalent to 20-30A of Si0 2 . Therefore, it extremely important to consider high dielectric constant materials of equivalent electrical thickness that are capable of sustaining a substantial voltage difference between the gate electrode and the Si-substrate [1,2]. The problems that these high-k materials suffer from include unacceptable levels of interface trap states (Dt) [3], bulk fixed charge (Qf), low Si interface carrier mobility, and 403 Mat. Res. Soc. Symp. Proc. Vol. 567 © 1999 Materials Research Society