ADVANCED SYNTHESIS OF DSP ALGORITHMS IN MODERN PROGRAMMABLE ARCHITECTURES Tadeusz Łuba, Mariusz Rawski, Paweł Tomaszewicz Institute of Telecommunications, Warsaw University of Technology, Nowowiejska 15/19, 00-665 Warsaw, Poland, e-mail: { luba, rawski, p.tomaszewicz }@tele.pw.edu.pl Abstract: In this paper, using FIR filters as an example, the discussion on efficiency of different implementation methodologies used in DSP application targeted modern FPGA architectures is presented. Nowadays programmable technology provides possibility to implement digital system with use of specialized embedded DSP blocks. On the first place, however, this technology gives the designer the possibility to increase efficiency of designed system by exploitation of parallelisms of implemented algorithms. Moreover, it is possible to apply special techniques, such as distributed arithmetic (DA). Since in this approach general purpose multipliers are replaced by combinational LUT blocks, it allows constructing digital filters of very high performance. Additionally, application of the functional decomposition based method to LUT blocks optimisation and mapping has been investigated. The paper presents results of comparison of different design approaches. Copyright © 2006 IFAC Keywords: Digital signal processors, FPGA, Logic synthesis, Functional decomposition. 1. INTRODUCTION Digital-signal processing (DSP), thanks to explosive growth in wired and wireless networks and in multimedia, represents one of the hottest areas in electronics. Within the next few years we can anticipate more wireless and digital communication standards, pervasive computing and widespread availability of data on the move. Therefore the growing requirements for processing speeds of the order of 10-100 billions of operations per second, the need for rapid prototyping and software definable architectures will further penetration of FPGAs into the DSP communication. In recent years digital filters have been recognised as primary digital signal processing operation. With advances in digital technology they are rapidly replacing analogue filters, which were implemented with RLC components. Digital filters are typically implemented as multiply-accumulate (MAC) algorithms with use of special DSP chips (Lapsley, et al., 1997; Lee, 1988; Lee, 1989). When one speaks of a DSP chip, one perceives of an off-the-shelf chip, which has an architecture designed to efficiently execute math-intensive DSP algorithms. Such devices are based on concept of RISC processors with an architecture consisting fast array multipliers. By using pipeline architecture the speed of such implementation is limited by the speed of array multiplier. But there are several other chip types that are better choices for specific DSP implementations. Recent reductions in the cost of high-density FPGAs, combined with advances in software-oriented FPGA design tools, have led to a corresponding rise in the use of these devices to handle functions that are traditionally the domain of DSP processors, while at same time dramatically reducing the risks and up- front costs of custom ASIC solutions. Nowadays, by taking advantage of the opportunities provided by programmable digital devices, we are able to build very complex digital circuits and systems at relatively low cost in a single programmable structure. Field programmable gate arrays now possess sufficient performance and logic capacity to implement a number of digital signal processing algorithms effectively.