Analytical modeling and simulation of subthreshold characteristics of back-gated SSGOI and SSOI MOSFETs: A comparative study Mirgender Kumar a, * , Sarvesh Dubey a , Pramod Kumar Tiwari b , S. Jit a a Department of Electronics Engineering, Indian Institute of Technology (Banaras Hindu University), Varanasi 221005, Uttar Pradesh, India b Department of Electronics and Communication Engineering, National Institute of Technology, Rourkela 967008, India article info Article history: Received 21 March 2013 Received in revised form 9 July 2013 Accepted 11 July 2013 Available online 20 July 2013 Keywords: Strained-Si-on-SiliconeGermanium-on- Insulator (SSGOI) Strained-Si-on-insulator (SSOI) Threshold voltage Subthreshold current and subthreshold swing EI factor abstract The SiliconeGermanium-on-Insulator (SGOI) and Silicon-on-Insulator (SOI) based MOS structures are spearheading the strained-Si technology. The present work compares the subthreshold characteristics of two short-channel back-gated (BG) strained-Si-on-SGOI (SSGOI) and BG strained-Si-on-Insulator (SSOI) MOSFETs, and provides some solutions to overcome the degradation in subthreshold characteristics with the unrelenting downscaling of the devices. Subthreshold behaviors of the MOS structures are based on surface potential model which is determined by solving the 2D Poisson’s equation with suitable boundary conditions by evanescent mode analysis for both of the MOS structures. The closed form ex- pressions for threshold voltage, subthreshold current and subthreshold swing have been derived for symmetrical as well as independent gate operation (IGO). In addition, the Electrostatic integrity (EI) factors for SSOI and SSGOI MOS structures have been estimated and compared with Double-Gate (DG) MOSFET. The numerical simulation results, obtained by ATLASÔ, a 2D device simulator from Silvaco, have been used to assess the validity of the models. Ó 2013 Published by Elsevier B.V. 1. Introduction Shrinking of CMOS device dimension has been persistently quenching the everlasting requirement of faster computers since its inception. The scaling of CMOS devices fabricated on a bulk silicon substrate has almost reached its bottleneck and the search for a viable alternative to this classical CMOS structure has been becoming an important challenge to scientists and researchers [1,2]. Moreover, the relentless scaling of CMOS devices has severely undermined the subthreshold characteristics due to short geome- try effects (SGEs) at nanoscale. As a remedial measure, ultra-thin gate dielectrics [3] and ultra-shallow source/drain junctions [4] in MOS structures are being utilized to improve the gate control over channel and immunity against SGEs respectively. To some extent, channel doping techniques such as halo implants [5], vertical trapezoidal doping [6], highly doped channel [7], laterally asym- metric doping profile [8] and graded band gap channel [9] are re- ported worthy to alleviate the electrical characteristics of the device. In recent years, some of the advanced MOS structures like multi-material gate structures [10] and multi-gate structures [11] are being extensively studied for better immunity against severe SGEs at very short-channel lengths. However, fewer of the afore- mentioned techniques are preferred for mass production because of very tedious processing steps and fundamental physical limita- tions, which may limit the further scaling. The higher channel doping is less preferential as it causes mobility reduction due to higher Coulomb scattering rates [12]. In the light of these facts, the improvement in device performance with scaling is becoming a challengeable task, which however could be achieved by increasing the carrier mobility. High mobility makes the carrier to travel faster with concurrent improve in device performance making the scaling less mandatory [13]. Various materials other than silicon have been proposed for increasing the carrier mobility in the channel region of MOSFETs but these suffers from reliability issues compared to well estab- lished Si CMOS technology [14,15]. Lattice deformation, apart from changing the channel material, has been found a sound approach for achieving higher carrier mobility. It has been reported that strain caused by lattice deformation can enhance the carrier mobility up to 35% because of its tangible effects on band structure and the carrier transport [16e18]. Strained-Si technology renders enhanced switching speed, improved short-channel-effects (SCEs) and reduced parasitic capacitance [19,20]. * Corresponding author. Tel.: þ91 5426701257; fax: þ91 5422366758. E-mail addresses: mkumar.rs.ece@iitbhu.ac.in, mkshekhawat22@gmail.com (M. Kumar). Contents lists available at ScienceDirect Current Applied Physics journal homepage: www.elsevier.com/locate/cap 1567-1739/$ e see front matter Ó 2013 Published by Elsevier B.V. http://dx.doi.org/10.1016/j.cap.2013.07.013 Current Applied Physics 13 (2013) 1778e1786