Vol.:(0123456789) 1 3 Journal of Computational Electronics https://doi.org/10.1007/s10825-019-01421-4 Design and evaluation of clocked nanomagnetic logic conservative Fredkin gate Ali Akbar Dadjouyan 1  · Samira Sayedsalehi 2  · Reza Faghih Mirzaee 3  · Somayyeh Jafarali Jassbi 1 © Springer Science+Business Media, LLC, part of Springer Nature 2019 Abstract Nanomagnetic logic (NML) has recently been proposed as an attractive and promising implementation of QCA and also as a possible alternative to the CMOS technology. With this emerging technology, it is possible to process and store binary information according to the magnetization state of nanomagnets. Similar to other nanotechnologies, NML circuits are also sensitive to fabrication variations and thermal fuctuations. Therefore, it is highly consequential to improve the testability of these circuits. Circuits based on conservative logic inherently enhance test performance. In this paper, the Fredkin gate, which is one of the most famous conservative reversible gates has been designed and simulated in NML by considering the physical properties of nanomagnets. It can be used to design other testable and ultra-low-power NML circuits as well. OOMMF physical simulation tool is used to simulate and validate the proposed gate at room temperature. The results indicate the correct functionality of the design. Keywords Nanotechnology · Field-coupled nanocomputing · Nanomagnetic logic · Conservative logic · Reversible logic · Fredkin gate · NML clocking 1 Introduction Conventional CMOS circuits have recently faced some challenges especially in nanoscale such as short channel efects, reduced gate controllability, and high leakage cur- rent density. The introduction of nanoscale devices such as nanomagnet logic (NML) has led to a promising solution for dealing with these challenges and difculties [1, 2]. NML is based on the feld-coupled nanocomputing principle that uses bistable and single-domain nanomagnets for storing, processing, and transferring data. Due to the magnetic nature of this emerging technology, NML circuits have very low power consumption [3, 4]. Moreover logic and memory can be combined with each other in the same device [5]. In addition, their high resistance to radiation and heat also makes them suitable for the employment in harsh operating environments [6, 7]. Finally, these circuits can operate at room temperature because of their relatively large magnetic energies [8]. Due to these special advantages, NML could be considered as an alternative or a complementary logic device to the customary CMOS technology. NML circuits, like many other nanoscale circuits, are subject to process and environmental variations. Irregular distances between nanomagnetic cells, missing cells, and merging nanomagnets are the most common defects [9], each of them afects the energies of nanomagnets and their switching behavior, and consequently infuences the overall performance of NML circuits [10]. Thermal fuctuation is another factor that might change the switching of nanomag- nets [11, 12]. As a result, the design of testable NML circuits is of great importance. Error detection is one of the primary tasks in test process either immediately after fabrication or during normal circuit operation. Thus, if the techniques that facilitate error detec- tion are used, the efciency of the test process as well as the fault tolerance will be increased. One of the difculties with error detection in conventional circuits made from conven- tional gates is that they do not have the inherent capability of error detection and their designs need to be modifed in order * Samira Sayedsalehi s_sayedsalehi@azad.ac.ir 1 Department of Computer Engineering, Science and Research Branch, Islamic Azad University, Tehran, Iran 2 Department of Computer Engineering, South Tehran Branch, Islamic Azad University, Tehran, Iran 3 Department of Computer Engineering, Shahr-e-Qods Branch, Islamic Azad University, Tehran, Iran