Design and Implementation of Radix 4 Based Multiplication on FPGA Supriya S. Saste 1 Dept. of Electronics & Telecommunication Trinity College of Engineering & Research Pune, India. Prof. Anil G. Sawant 2 Dept. of Electronics & Telecommunication Trinity College of Engineering & Research Pune, India. Abstract— With the recent rapid increase in scale of integration, many sophisticated signal processing as well as video processing systems are being implemented on VLSI chip in which multiplication is dominant operation. The performance of these systems is based on computation capacity and power consumption. This paper presents novel approach of multiplication scheme based on Radix 4 and its implementation on FPGA which results in great computational capacity and reduced power consumption. This system has been designed and simulated using Xilinx 13.4 for 8x8 bit numbers. Key Words—Booth’s Algorithm, Radix 4, VLSI, Xilinx 13.4. I. INTRODUCTION Multiplication is one of the most important arithmetic operations which is used in high performance systems such as microprocessors, digital signal processors and multimedia applications [1][2][5]. Previously multiplication was done by repetitive sequence of other two basic arithmetic operations viz., addition, subtraction along with shift operations. Hence, multiplication is repetitive addition of numbers. The ‘multiplicand’ is a number which is to be added and number of times it is added is called as ‘multiplier’. The repetitive addition method to employ multiplication is comparatively slow. Multiplication is mainly performed in three different stages: In first stage partial products are generated. The next stage i.e. stage two deals with reduction of partial products and finally in stage three all the partial products are summed together to get the final result of multiplication operation. The fundamental principle of multiplication is generation of partial products and accumulation of partial products [2]. Multiplication can be performed both on signed as well as unsigned numbers [3]. However signed multiplication is careful operation. Signed numbers cannot be multiplied in same manner as that of the unsigned numbers. Here the Booth’s algorithm comes in. The motivation of Booth’s multiplication scheme i s to increase the speed of multiplication process. As compared to conventional methods Booth’s multiplication helps to reduce the number of iteration steps and results in faster computation. In this paper we present 8 bit multiplication by using modified Booth’s (Radix 4) algorithm and its implementation on hardware platform. II. BOOTH’S RECODING (RADIX 2) ALGORITHM The Booth’s algorithm was invented by Andrew D. Booth which employs multiplication of both signed and unsigned numbers. This algorithm has been used to generate the partial products which firstly encode the multiplier bits. Radix-2 and Radix-4 are two algorithms which generate reduced and efficient partial products for multiplication [3]. The basic technique stated by Booth is explained further. The technique invented by Booth allows for smaller and faster multiplication of binary integers in 2’s complement representation. In order to do multiplication by Booth’s recoding algorithm, we have to recode the multiplier first. Each bit of the recoded multiplier can take any value from: 0, 1 and -1. In order to do this, 2 bits of multiplier are compared at a time by overlapping technique. Thus, in Radix-2 grouping of multiplier bits starts from LSB for which the first block uses only single bit of multiplier and another bit is assumed zero [4]. The recoded multiplier for Radix-2 is obtained by performing following steps: i) Add a zero to the LSB side of given multiplier. ii) By using overlapping technique, group two bits of multiplier and recode the number using following table: TABLE I. RADIX-2 BOOTH ENCODING Xn Xn+1 Recoded Bits Operations Performed 0 0 0 0 0 1 +1 1*Multiplicand 1 0 -1 -1*Multiplicand 1 1 0 0 Consider following example in which multiplicand and multiplier have 4 bits. Multiplicand 1100 Multiplier 1010 So, according to the table shown above the recoding bits will be obtained as partial product: PP0=00000 PP1=00100 PP2=11100 PP3=00100 Finally, all the partial products are added to get final product result. The main version of Booth’s algorithm (Radix-2) had two drawbacks: 1) With the invariability of add/subtract operations, the algorithm became inconvenient while designing parallel multipliers. 2) If there is a string of isolated 1s, the algorithm becomes inefficient [10]. International Journal of Engineering Research & Technology (IJERT) ISSN: 2278-0181 http://www.ijert.org IJERTV5IS090557 Vol. 5 Issue 09, September-2016 (This work is licensed under a Creative Commons Attribution 4.0 International License.) Published by : www.ijert.org 619