RESEARCH ARTICLE FPGA implementation of highly secure, hardware‐efficient QC‐ LDPC code–based nonlinear cryptosystem for wireless sensor networks Celine Mary Stuart | P. P. Deepthi Department of Electronics and Communication Engineering, National Institute of Technology Calicut, Kerala, India Correspondence Celine Mary Stuart, Department of Electronics and Communication Engineering, National Institute of Technology Calicut, PIN‐673601, Kerala, India. Email: celinemarystuart@gmail.com Summary This paper presents the design and implementation of an integrated architecture for embedding security into quasi‐cyclic (QC) low‐density parity‐check (LDPC) code– based cryptographic system through a nonlinear function of low hardware complex- ity. Instead of using standard S‐boxes for implementation of nonlinear function, this paper considers a method on the basis of maximum length cellular automata (CA), so that enhanced security can be achieved with simple hardware structure. The pro- posed system adopts a lightweight random bit stream generator on the basis of linear feedback shift register (LFSR) for generating random error vectors, so that a large number of vectors with very good cryptographic properties can be made available with low hardware cost. Different permutation patterns generated for different mes- sage blocks help to provide good degrees of freedom for tuning security with reason- able key size. The hardware architecture for the proposed system is developed and validated through implementation on Xilinx Spartan 3S500E. Analytical and synthe- sis results show that the proposed scheme is lightweight and offers very high security through continuously changing parameters, thus making it highly suitable for resource‐constrained applications. KEYWORDS cellular automata, cryptosystem, ECBC, LFSR, QC‐LDPC code 1 | INTRODUCTION Error control and security are 2 important requirements in modern digital communication systems. The extensive use of high‐speed wireless communication systems has hastened the demand for reliable and secure data transmission. Imple- mentation of conventional cryptography algorithms demands high processing capabilities and high power requirements. Because, many of the emerging wireless networks are constrained in resources, especially in power, there is a great need to enhance security without compromising computa- tional and hardware cost. One of the recent developments in wireless technology known as wireless sensor networks (WSNs) 1–4 deployed for many real‐life applications espe- cially in military, habitat monitoring, health care, etc is gaining increased popularity. The demand on secrecy and reliability in communication is very high for these applica- tions. Due to resource constraints, WSNs make use of light- weight symmetric key algorithms to secure the data. The weaker cryptographic methods employed in them for saving power makes them easy targets of the attacker. The sensors that are deployed in large quantities in an adversarial and unattended environment 2 face great security challenges. Recent research 5,6 has shown that embedding security in the channel code could be used to enhance the security of the entire system, without compromising requirements on reli- ability and power efficiency. The 2 channel coding schemes which provide near Shannon‐limit performance and allow key‐based designs are Turbo codes and LDPC codes. The LDPC codes provide more degrees of freedom for security in design compared to Turbo codes because Turbo code provide option to embed Received: 12 February 2016 Revised: 19 September 2016 Accepted: 25 September 2016 DOI 10.1002/dac.3233 Int J Commun Syst 2016; 1–16 Copyright © 2016 John Wiley & Sons, Ltd. wileyonlinelibrary.com/journal/dac 1