This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1 High-Precision PLL Delay Matrix With Overclocking and Double Data Rate for Accurate FPGA Time-to-Digital Converters Poki Chen , Member, IEEE, Jian-Ting Lan, Ruei-Ting Wang, Nguyen My Qui, John Carl Joel S. Marquez, Student Member, IEEE, Seiji Kajihara, Member, IEEE, and Yousuke Miyake, Member, IEEE Abstract—An extremely high-resolution, 2-D Vernier field- programmable gate array (FPGA) time-to-digital converter (TDC) with phase wrapping and averaging has been proposed recently to get an extremely fine resolution of 2.5 ps. However, the cell delays in a delay matrix are not fully controlled so that the TDC performance strongly depends on the stochastic distribution of cell delays, and the input range is limited to less than 20 ns. To achieve both high-precision phase division and wide measurement range, a phase-locked loop (PLL)-based delay matrix, which is capable of overclocking and double data rate (DDR), is proposed in this article. All delay cells are under the precise control of PLLs to generate output phases evenly divided within the reference clock period. For a concept proof, the TDC architecture is implemented on an Altera Stratix-IV FPGA chip to achieve 15.6-ps resolution. The differential nonlin- earity (DNL), integral nonlinearity (INL), and rms resolution are measured to be merely -0.157 to 0.137 LSB, -0.176 to 0.184 LSB, and 1.0 LSB, which prove the superiority of the proposed structure to its stochastic counterparts. The proposed high-precision phase division technique can be applied to not only the TDC but also the digital-to-time converter (DTC) to enrich its future applications. Index Terms—2-D Vernier, delay matrix, double data rate (DDR), overclocking, phase division, phase-locked loop (PLL), time-to-digital converter (TDC). I. I NTRODUCTION T ECHNOLOGY development has increased the need to measure the start–stop time intervals of physical events and convert them into digital formats. These measurements are Manuscript received July 22, 2019; revised October 12, 2019 and December 1, 2019; accepted December 17, 2019. This work was supported in part by the Ministry of Science and Technology under Grant MOST 107- 2221-E-011-110, in part by the National Taiwan University of Science and Technology, and in part by the Kyushu Institute of Technology under Grant Kyutech-NTUST-106-02. (Corresponding author: Poki Chen.) Poki Chen, Ruei-Ting Wang, Nguyen My Qui, and John Carl Joel S. Marquez are with the Department of Electronic and Computer Engineering, National Taiwan University of Science and Technology, Taipei 10617, Taiwan (e-mail: poki@mail.ntust.edu.tw). Jian-Ting Lan is with Himax Technologies Inc., Tainan 74148, Taiwan (e-mail: m10502207@gapps.ntust.edu.tw). Seiji Kajihara and Yousuke Miyake are with the Kyushu Institute of Technology, Fukuoka 804-0015, Japan (e-mail: kajihara@cse.kyutech.ac.jp; miyake@aries30.cse.kyutech.ac.jp). Color versions of one or more of the figures in this article are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TVLSI.2019.2962606 performed by the so-called time-to-digital converter (TDC). In addition to the inherent applications, such as nuclear physics, biomedical engineering, and time-of-flight measure- ment [1]–[3], TDCs are also applied in design-for-testability such as on-chip delay, temperature, and voltage measurements [4] and [5]. They are even used to test transistor aging by measuring the increased delay due to aging [6]. To achieve high resolution, fine measurement techniques or the so-called interpolators are adopted to design TDCs. Analog interpolators, such as time-stretching [7] and time-to-amplitude conversion [8], are proposed. However, they are quite sensitive to process, voltage, and ambient temperature (PVT) variations and undergo long conversion time. Consequently, digital techniques such as tapped delay lines (TDLs) [9], pulse shrinking delay cell [10], gated ring oscillators [11], and 2-D Vernier [12] are commonly used. Most of the current TDCs based on digital interpolators are implemented with full-custom designs to get good linearity, as well as high resolution down to a picosecond order. A 2-D Vernier with second-order 16 modulators and a spiral 2-D arbiter array [13] is adopted to achieve a resolution of 1 ps and differential nonlinearity (DNL)/integral nonlinearity (INL) of 0.41/0.79 ps at the expense of long conversion time. A TDC based on pulse shrinking mechanism [14] obtains 1.8-ps resolution. However, it suffers from a low conversion rate. The time amplifier, which is based on two switched ring oscillators [15], is proposed to accomplish 2.6-ps resolution and increase power efficiency. However, it is limited to a short dynamic range. Moreover, a 13-bit TDC based on cyclic time-domain successive approximation [16] is proposed to achieve 0.61-ps resolution and 5 ns dynamic range. This structure increases the conversion time and requires highly accurate matching for offset delay in two loops. Another TDC using stochastic phase interpolation fabricated on a 14-nm fin field-effect transistor (FinFET) [17] achieves 1.17-ps resolution but short measurement range. Although full-custom TDC designs are better than their field-programmable gate array (FPGA)-based counterparts in performance, they require rigorous design and verification process. In contrast to the application-specified integrated circuit (ASIC), FPGA with parallel architecture has shorter 1063-8210 © 2020 IEEE. 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