744 IEICE TRANS. ELECTRON., VOL.E95–C, NO.4 APRIL 2012 PAPER An Energy-Efficient Full Adder Cell Using CNFET Technology Mohammad Reza RESHADINEZHAD †∗ a) , Member, Mohammad Hossein MOAIYERI † , Nonmember, and Kaivan NAVI †b) , Member SUMMARY The reduction in the gate length of the current devices to 65 nm causes their I-V characteristics to depart from the traditional MOS- FETs. As a result, manufacturing of new efficient devices in nanoscale is inevitable. The fundamental properties of the metallic and semi-conducting carbon Nanotubes (CNTs) make them alternatives to the conventional silicon-based devices. In this paper an ultra high-speed and energy-efficient full adder is proposed, using Carbon Nanotube Field Effect Transistor (CN- FET) in nanoscale. Extensive simulation results using HSPICE are reported to show that the proposed adder consumes lower power, and is faster com- pared to the previous adders. key words: CNFET,Full adder, High performance, low power, nanotech- nology 1. Introduction The complexity of the integrated circuits, with respect to minimum component cost, doubles every 24 months. This statement, formulated approximately forty years ago, is known as Moore’s low. The reduction in physical gate length to below 65 nm leads to serious challenges such as large parametric variations, reduced gate control and an ex- ponential increase in leakage current. Because of the lim- itations stated, researchers became eager to focus on new emerging technologies to replace conventional silicon and current MOSFET-based [1]. Carbon nanotube field effect transistor (CNFET) is the most promising technology to ex- tend or complement the traditional silicon technology. Due to the similar operation principle and the device structure of CMOS and CNFET devices, we can reuse the established CMOS design infrastructure and CMOS fabrication process in the CNFET technology [2]. Moreover, the most important reason is that CNFET has the best experimentally demon- strated device current carrying ability to date [3]. There has been some work done based on CNFETs, such as arithmetic circuits, multiple valued logic circuits and interconnection networks [2]–[8]. Addition/Subtraction is one of the basic structures in many VLSI systems such as microprocessors, digital computing and signal process- ing systems and nano-micro system [9], [10]. Manuscript received July 31, 2011. Manuscript revised November 11, 2011. † The authors are with the Department of Electrical and Com- puter engineering, Shahid Beheshti University, G.C., Tehran, Iran. ∗ Presently, with the Department of Computer Engineering, University of Isfahan, Isfahan, Iran. a) E-mail: m reshadi@sbu.ac.ir b) E-mail: navi@sbu.ac.ir DOI: 10.1587/transele.E95.C.744 The full adder is one of the most important units in arithmetic circuits, and its performance could affect the ef- ficiency of the whole system. Consequently, it is in the in- terest of researchers to come up with a full adder structure with a higher performance and lower power consumption. In this paper we offer design details of an ultra-low power- delay product full adder cell based on Nanotube technology. This CNFET-based full adder offers low latency and high throughput. The organization of the paper is as follows: in Sect. 2 an overall review of carbon Nanotube field effect transis- tors will be introduced. In Sect. 3, first we will introduce previous adder designs that have been implemented using either CMOS technology or CNTFET technology. Then in the second part of this section, we explore the proposed full adder cell implementation. In the next section we dedicate ourselves to an extensive simulation results and comparison with the classical state-of-art CMOS and CNFET-based full adders. Finally, Sect. 5 contains our concluding remarks. 2. Carbon Nanotube Field Effect Transistors (CN- FETs) Carbon nanotube is theoretically defined as a folded sheet of carbon, called graphite. According to how to fold the graphite sheet, the final nanotube will have different band- gap and consequently various electrical properties. Depend- ing on the cut, there exist three different kinds of nanotube; Zigzag, Armchair and Chiral. Based on the number of coaxial tubes shaping the nanotubes, they are categorized as single-wall (SWCNT) or multi-wall (MWCNT) each has distinguished properties for different applications. A single- walled carbon nanotube (SWCNT) can be visualized as a single sheet of graphite which is rolled up and joined to- gether along a wrapping vector Ch = n 1 . a 1 + n 2 . a 2 , where   a 1 , a 2  are the lattice unit vectors, and the indices (n 1 , n 2 ) are positive integers that specify the tube’s structure [11]. The nanotube is metallic if n 1 = n 2 or n 1 - n 2 = 3q(q ∈ Z), otherwise, the tube is semiconducting [12]. Thus, roughly one-third of chiral tubes are metallic and two-thirds are semiconducting. In a carbon nanotube field effect transistor (CNFET), the channel between the source and the drain is an individual semiconducting single-walled carbo nanotube. The first such device was produced by the Dekker group in 1998 [13]. Since a = |a 1 | = |a 2 | = 0.246 nm, the magni- Copyright c  2012 The Institute of Electronics, Information and Communication Engineers