Analytical modelling and design of 9T SRAM cell with leakage control technique Jitendra Kumar Mishra 1 • Harshit Srivastava 1 • Prasanna Kumar Misra 1 • Manish Goswami 1 Received: 24 February 2019 / Revised: 24 February 2019 / Accepted: 19 June 2019 Ó Springer Science+Business Media, LLC, part of Springer Nature 2019 Abstract This paper presents a novel 9T static random access memory (SRAM) cell consisting of a single ended isolated read bit line with 2T read port for improving stability and a tail transistor for saving power. In the proposed design owing to the use of separate bitlines, the storing node voltage has not been affected during active mode operation. In the idle (hold) mode the static power dissipation of SRAM cell has been drastically reduced due to the formation of stack between tail transistor and internal latch. The proposed design has been verified by cadence virtuoso tool using UMC 65 nm CMOS technology. It provides a 42% and 34% improvement in write stability when compared to basic 6T and ultralow voltage (UV) 9T SRAM cells respectively. It has been observed that, the read stability is improved by 12% when compared to basic 6T SRAM cell and penalty of 10% when compared to UV 9T SRAM cell. A reduction of 22% in static power dissipation has also been observed in proposed design as compared to basic 6T SRAM cell when designed at same technology. This paper has also been proposed a mathematical modelling for validating the proposed design. Keywords Mathematical modelling  Read port  SRAM  Stacking effect  Static power dissipation  Write and read stability 1 Introduction SRAM cell is widely used in portable devices like laptop, smart phones, biomedical instruments and other digital applications. It is a crucial digital macro and occupies major part of chip area [1]. To maintain the portability of the system, reduction in chip area is required which necessitate the need of scaling. The scaling of devices in deep sub micro-meter technology nodes has become a significant challenge towards maintaining the performance of digital system [2]. Power dissipation is one of the important performance parameter and the major part of power in such system is dissipated by SRAM [3], which then necessitate the need to reduce the power consumption of SRAM. Besides this, due to downscaling of technology node, the conventional six transistor (6T) SRAM cell also faces various issues like power dissipation, read stability, write stability, leakage current, bitline leakage, variability etc. [4, 5]. The reduc- tion in the supply voltage decreases the power consumption to a certain extent but it also degrades the stability of SRAM cell. Moreover, due to scaling of supply voltage, the read failure (during read operation data stored in storing nodes get flip) and write failure too occurs in basic 6T SRAM cell [6]. To overthrow the problem of read stability, many SRAM cell designs have been proposed with some additional circuitry, including 8T SRAM cell, separate 2T read port [7], 9T SRAM cell [8–10], 10T SRAM cell [11] etc. Also numerous write assist technique like, Vdd col- lapse, negative bit line, boosted Vss and wordline boosting technique [12–16] etc. have been proposed. In 9T SRAM cell, A. Teman et al. [10] had implemented a separate read port for improving read stability and separate feedback path for improving write stability. However supply feed- back 9T SRAM cell faces power dissipation issues. A disturb free 9T SRAM cell by Tu et al. [8] had also been implemented with a separate read port to improve the read stability and negative bit line technique for improving write ability has also been implemented. However due to & Manish Goswami manishgoswami@iiita.ac.in; rse2016506@iiita.ac.in 1 Department of Electronics and Communication Engineering, Indian Institute of Information Technology, Allahabad, India 123 Analog Integrated Circuits and Signal Processing https://doi.org/10.1007/s10470-019-01483-1