An On-line Test Strategy and Analysis for a 1T1R Crossbar Memory Manuel Escudero-Lopez, Francesc Moll and Antonio Rubio Electronics Engineering Department Universitat Politecnica de Catalunya Barcelona, Spain manuel.escudero@upc.edu, francesc.moll@upc.edu, antonio.rubio@upc.edu Ioannis Vourkas Dept. of Electrical Engineering Pontificia Universidad Catolica de Chile Santiago, Chile iovourkas@uc.cl Abstract—Memristors are emerging devices known by their nonvolability, compatibility with CMOS processes and high density in circuits density in circuits mostly owing to the crossbar nanoarchitecture. One of their most notable applications is in the memory system field. Despite their promising characteristics and the advancements in this emerging technology, variability and reliability are still principal issues for memristors. For these reasons, exploring techniques that check the integrity of circuits is of primary importance. Therefore, this paper proposes a method to perform an on-line test capable to detect a single failure inside the memory crossbar array. I. I NTRODUCTION Resistive switching devices (memristors) are emerging elec- tronic devices that are receiving significant attention because of their promising properties including being passive non- volatile memory elements, storing data in the form of re- sistance. Altough they were postulated by L. Chua back in 1971 [1], Chuas theory was connected with practice only in 2008 [2]. Some other interesting characteristics of memristors are the compatibility with CMOS technology and the highest possible device integration density [3]. It is expected that memristive device speed could match that of CMOS devices. Nonetheless, currently it isn’t a mature enough technology and there is space for improvement in several aspects. For instance, variability and reliability are considered among the most critical issues [4]. Memristors are suitable devices for applications such as memories and computing, both digital and analog. As mem- ristors are nonvolatile, they are ideal to store data even when not powered. This feature and their potential high device density are two key properties for memory applications. How- ever, variability and reliability must be controlled in these applications and strategies to cope with these issues must be developed. On-line testing is a useful technique as memristors may fail eventually due to its improvable reliability. There are some works about on-line testing circuits with memristor crossbars; e.g. [5] applies design for testability to detect open faults in crossbar, whereas [6] takes advantage of sneak-path currents to perform the testing procedure faster and [7] designs to detect bridge defects. In this context, our work presents a simple fault model for a single one transistor one memristors (1T1R) cell more focused in the possible malfunction of the cell devices than the previous works, as well as the interferences between cells when faults occur and a method to detect them during the system normal operation. The paper is organized as follows. Section II introduces the device model used in the work, Section III depicts the memory system, Section IV shows the fault model considered, Section V presents the on-line test procedure and Section VI shows the simulation results. Finally, Section VII concludes the paper. II. MEMRISTOR FUNDAMENTALS IN BRIEF The memristor is a passive two-terminal device, a passive circuit element with a characteristic parameter named memris- tance. Memristance is conceptually defined as the derivative of flux with respect to electric charge, but it is commonly explained as a resistance that depends on the previous his- tory of the electric charge that passes through it. There are different types of memristors: bipolar or unipolar, filamentary or homogeneous switching [8]. For instance, in the resistive RAM (ReRAM) device assumed in this paper, the change in its memristance is attributed to the creation or destruction of one or more conductive filaments inside the metal-insulator- metal device structure (in line with the soft breakdown of an oxide intermediate layer). The memristor model adopted in this work is presented in [9]. The model is based on the formation of a two-dimensional conductive filament, described as a cylinder that modulates its length and width according to the voltage applied to the termi- nals of the device. It features variability, parasitic elements and temperature effects, among other features. The used parameter values have been extracted from TiN/HfOx/TiOx/Pt devices of 10 nm feature size. The typical I-V pinched curve observed in memristors is shown in Figure 1, where V M and I M are the voltage across the memristor and the flowing current, respectively. The I/V curve was generated using a triangular signal of amplitude 2 V and period 40 ns. The memristor switches to low resistive state (LRS) when a positive voltage is applied. Then a negative voltage gradually increases the memristance, finally leading to a high resistive state (HRS). In a memory application memristors are tipically excited with voltage pulses. The width and voltage level are important to achieve desired resistance states. A long, high voltage pulse is needed to bring the memristor to a given state, while a