Flexibility-oriented Design Methodology for Reconfigurable ΔΣ Modulators Pengbo Sun, Ying Wei, Alex Doboli Department of Electrical and Computer Engineering, State University of New York at Stony Brook, Stony Brook, NY, 11794-2350 psun, ywei, adoboli@ece.sunysb.edu Abstract This paper presents a systematic methodology for pro- ducing reconfigurable ΔΣ modulator topologies with opti- mized flexibility in meeting variable performance specifica- tions. To increase their flexibility, topologies are optimized for performance attributes pertaining to ranges of values rather than being single values. Topologies are imple- mented on switched-capacitor reconfigurable mixed-signal architectures. As the number of configurable blocks is very small, it is extremely important that the topologies use as few blocks as possible. A case study illustrates the method- ology for specifications from telecommunications area. 1. Introduction Reconfigurable systems aim to simultaneously offer the two main advantages of hardware and software: (i) simi- lar to application-specific hardware, to provide high perfor- mance processing, and (ii) similar to software, to be flexible enough in tackling different applications. Reconfigurable systems are attractive implementation platforms for many embedded applications due to their capability of offering low development costs and short design times, while being accessible to less experienced designers. While reconfigurable digital systems are very popular and well understood in terms of their capabilities and limi- tations, reconfigurable analog and mixed-signal (AMS) sys- tems are - in contrast, much less studied or employed in practical applications. This prevents the more comprehen- sive harvesting of the possible benefits of reconfigurable systems, as the majority of embedded applications (e.g., embedded control and telecommunications) include signif- icant amounts of analog signal processing. To tackle this major limitation, research must not only address new re- configurable AMS architectural concepts, but also study the related design methodologies and EDA tools. More specif- ically, it is essential to develop efficient techniques for de- signing reconfigurable analog to digital converters (ADC) due to the importance of ADCs in embedded systems. Several general-purpose reconfigurable AMS architec- tures are mentioned in the literature [3, 13]. Continuous- time and switched-capacitor reconfigurable ADCs have been presented in [4, 8, 12], but no design methodology or EDA tools were considered. More recently the PSoC reconfigurable mixed-signal array has been offered by Cy- press Inc. [5, 15] as a cost-effective solution to embedded system implementation. While several ADCs have been implemented using PSoC [16], there is no design method- ology and there are no EDA tools that would allow effort- less and rapid design of new ADCs. Various techniques for single-mode (non-reconfigurable) ΔΣ ADC design have been described in [2, 7, 11]. A systematic design flow for continuous-time reconfigurable ΔΣ ADCs has been re- cently proposed in [14]. However, the produced modula- tor topologies are restricted to a set of predefined perfor- mance specifications (e.g., GSM, CDMA, and UMTS com- munication standards). The topologies have no flexibility in addressing new performance specifications. This is an im- portant limitation because flexibility ought to be one of the main strengths of reconfigurable AMS architectures. This paper proposes a systematic design methodology for creating flexible reconfigurable ΔΣ modulator topolo- gies implemented on switched-capacitor (SC) reconfig- urable AMS architectures. The work considered an AMS architecture based closely on the PSoC reconfigurable ar- chitecture. As the amount of programmable analog blocks is very limited in PSoC, it is extremely important that the modulator topologies use as few blocks as possible. In con- trast to the existing work, the proposed methodology gen- erates a set of topologies that are optimized to meet perfor- mance attributes pertaining to ranges of values rather than being singular values. For example, the topologies are op- timized for dynamic range (DR) requirements in the range [DR min , DR max ], and bandwidth (BW) constraints in the range [BW min ,BW max ]. The produced topologies can ef- ficiently meet specifications SP ∈ [DR min , DR max ] × [BW min ,BW max ] while using minimum amount of hard- ware. In contrast, other design methodologies would pro- duce a single topology corresponding to the most con- 978-3-9810801-2-4/DATE07 © 2007 EDAA