I.J. Engineering and Manufacturing, 2019, 4, 33-44 Published Online July 2019 in MECS (http://www.mecs-press.net) DOI: 10.5815/ijem.2019.04.03 Available online at http://www.mecs-press.net/ijem Memory Controller and Its Interface using AMBA 2.0 Hitanshu Saluja a , Naresh Grover b a,b Department of Electronics & Communication, Manav Rachna International Institute of Research and Studies, Faridabaad, Hrayana, India Received: 15 January 2019; Accepted: 25 April 2019; Published: 08 July 2019 Abstract This paper elaborates the AMBA bus interface bridge between memory controller and other supporting peripheral. The work claims the integration with FIFO, RAM and ROM with slave interface and the master of AHB bus. The AHB master initiates the operation and generates the necessary control signal. Memory controller is implemented with finite state machine considering with all the peripheral works in synchronous mode. Despite these shortcomings of the work performed study and development that followed has led the development of a memory controller on AMBA-AHB bus at a very advanced stage and next to prototyping. VHDL code is utilized to develop the design and it is synthesized in Xilinx Virtex 6 device (XC6VCX75T). The design claims a minor area overhead with improvement in speed 185.134 MHz. Index Terms: AMBA, AHB Master, AHB Slave, SOC, Xilinx. © 2019 Published by MECS Publisher. Selection and/or peer review under responsibility of the Research Association of Mode rn Education and Computer Science 1. Introduction Technological developments in the world industrialization have allowed the integration of more and more functions on the same digital integrated circuit. Today, several microprocessors, hardware accelerators, communications systems diverse and with even operating systems. this allows therefore perform all the functions necessary to perform complex computer processing on the same chip, hence the birth of the concept of systems on chip (System on Chip), successors of specialized circuits ASIC (Application Specific Integrated Circuit) [1]. * Corresponding author. E-mail address: