Design of High Speed and Area efficient modified Kogge Stone Multiplier Using ZFL S Baba Fariddin 1 , Dr. Rahul Mishra 2 {sbabafariddin@gmail.com 1 , rahulmishra@aku.ac.in 2 } Research Scholar, Dept of ECE, Dr. A.P.J. Abdul Kalam University, Arandia, Indore, M.P, INDIA 1 Professor & H.O.D, Dept of ECE, Dr. A.P.J. Abdul Kalam University, Arandia, Indore, M.P, INDIA 2 Abstract. In the applications of digital signal processing, multipliers plays important role. Basically, Finite field multiplier is the easiest of all operations in the finite field and most frequently used operation in arithmetic’s. Hence in this paper the design of high speed and area efficient modified kogge stone multiplier is implemented. Multiplier and multiplicand are taken as input in this system. From both multiplier and multiplicand 1’s and 0’s are identified. Factoring technique is utilized to minimize switching energy and increase the speed of operation. Zeros finding logic will identify the zeros from obtained product. This product will be added using parallel prefix adder to minimize the area. Compared to ripple carry multiplier, kogge stone multiplier, the proposed kogge stone multiplier gives effective results. Keywords: Kogge Stone Multiplier, Zero’s Finding Logic, Factoring technique, Parallel Prefix adder. 1 Introduction With the most recent upgrades in the zone of compact advanced applications and remote correspondence, power utilization investigation and techniques of reduction has become as noteworthy as speed, cost, and dependability in the circuit configuration level [1]. Energy utilization factors, which decide the measure of scattered devices, impact basic structure issues, for example, bundling and cooling necessities, power supply lines and limit, and the quantity of circuits that can be incorporated in a chip. The energy utilization in a computerized CMOS (Complex Metal Oxide Semiconductor) circuit comprises of dynamic power consumption, static power utilization, and short circuits power utilization. The prevailing power utilization is typically from the dynamic power, which is utilized in charging hub capacitances. As this realizes that in the regions of system on chip and VLSI structures, the low power circuit plans is a significant issue. As the elements of transistors are contracted into the profound sub-micron area, the impact of static spillage flows turns out to be increasingly noteworthy. As the components of transistors are contracted into the profound sub-micron area, the impact of static spillage currents turns out to be progressively critical. This part of intensity utilization can be controlled by novel plan, yet is transcendently taken care by process of technique. Two zones that has the focal point of dynamic research is I3CAC 2021, June 07-08, Chennai, India Copyright © 2021 EAI DOI 10.4108/eai.7-6-2021.2308776