Abstract—Low-density parity-check (LDPC) codes have been shown to deliver capacity approaching performance; however, problematic graphical structures (e.g. trapping sets) in the Tanner graph of some LDPC codes can cause high error floors in bit-error- ratio (BER) performance under conventional sum-product algorithm (SPA). This paper presents a serial concatenation scheme to avoid the trapping sets and to lower the error floors of LDPC code. The outer code in the proposed concatenation is the LDPC, and the inner code is a high rate array code. This approach applies an interactive hybrid process between the BCJR decoding for the array code and the SPA for the LDPC code together with bit-pinning and bit-flipping techniques. Margulis code of size (2640, 1320) has been used for the simulation and it has been shown that the proposed concatenation and decoding scheme can considerably improve the error floor performance with minimal rate loss. Keywords—Concatenated coding, low–density parity–check codes, array code, error floors. I. INTRODUCTION DPC codes, as a class of capacity achieving codes, have found various applications in digital standards and technologies since their discovery [1]. Using iterative belief propagation techniques such as SPA, LDPC codes can be practically decoded in time-feasible manner linear to their block length [2]. However, decoding of some LDPC codes using conventional SPA suffers from a weakness in higher signal-to-noise ratios (SNR's) known as error floor [3], [4] which is exhibited as a sudden saturation in BER [3]. The error floor could be troublesome in some communication and data storage systems where BER as low as 10 −12 to 10 −15 is required. It has been found that trapping sets (or near-codewords) are the main cause of error floors in SPA decoding of LDPC codes over AWGN channel [3], [4]. Recently, many research efforts have been made to mitigate the error floor problem. Some code construction methods have been proposed to avoid trapping sets, thereby lowering the error floors [5], [6]. Trapping sets have sophisticated combinatorial properties and in general it is difficult to find deterministic solutions for lowering error floors through code construction. Other methods aim to lower the error floor by changing the structure of decoder [7]. Decoder-based strategies need a prior knowledge of the dominant trapping sets in a particular code through computer simulations or parity-check matrix properties, which is often difficult to obtain. Also, it should be noted that, for codes with small minimum distances, Mohammad Ghamari from University of Texas at El Paso, United States e- mail: mghamari@utep.edu undetected errors could contribute to high error floors as well [11]. Decoder-based methods such as bit pinning [9], and bit flipping [11] have been proposed which modify the Log Likelihood Ratio (LLR) values of certain node or check bits to avoid trapping sets. The bit positions might be known from code properties or can be guessed through trial and error [11]. In this work, we propose a concatenation of LDPC and array codes. In the decoding process, LLR values are interchanged between the LDPC decoder (SPA) and the array code decoder (BCJR). Within the LLR interchange, bit- pinning and bit-flipping techniques are used be improve the performance. A Margulis LDPC code of length 2640 and rate 0.5 has been used to prove the concept through simulation and it has been shown that the proposed concatenation scheme together with the interactive decoding and bit-pinning/bit- flipping techniques lower the error floor significantly. II. TRAPPING SETS AND ERROR FLOOR LOWERING TECHNIQUES A (ω, ν) trapping set is a set of ω variable nodes which induce a subgraph with ν odd-degree check nodes which may lead the decoder to error-trap situations from which the decoder cannot escape [3]. Each trapping set is associated with a critical number  (where ൑ ߥ) which is the minimum number of erroneous variable nodes in a trapping set that leads to decoder failure [8]. In any iteration of SPA, if at least  number of errors appear in a trapping set, the even-degree check nodes will become mis-satisfied, and the odd-degree check nodes which may be referred to as un-satisfied check nodes will trap the errors within the set, then the decoder fails to converge no matter how many iterations are performed. When an iterative decoder gets "trapped" by the subgraphs associated with trapping sets, if there exists a way to inform the decoder with great certainty the value of one or more of the bits in a trapping set, then the iterative decoder would stand a better chance at resolving the values of the other bits in the trapping set [9]. This procedure is somehow possible through bit-pinning idea; upon encoding, fix (or pin down) the value of bits for each trapping set of known. The decoder then sets the LLRs for these pinned bits to the maximum possible value. The expense for pinning down these bits is usually very small in code rate and length. Bit pinning is quite similar to code shortening which is to remove selected columns of the code’s parity-check matrix. Removing columns of H in the decoder design is equivalent to setting the corresponding LLR's to infinity, instead of a finite maximum value. In LDPC decoding, since the trapping sets depends on the decoder input Lowering Error Floors by Concatenation of Low-Density Parity-Check and Array Code Cinna Soltanpur, Mohammad Ghamari, Behzad Momahed Heravi, Fatemeh Zare L World Academy of Science, Engineering and Technology International Journal of Mathematical and Computational Sciences Vol:11, No:4, 2017 149 International Scholarly and Scientific Research & Innovation 11(4) 2017 scholar.waset.org/1307-6892/10006914 International Science Index, Mathematical and Computational Sciences Vol:11, No:4, 2017 waset.org/Publication/10006914