Global Interconnects in VLSI Complexity Single Flux Qantum Systems Tahereh Jabbari and Eby G. Friedman Department of Electrical and Computer Engineering University of Rochester Rochester, New York, 14627 tjabbari,friedman@ece.rochester.edu ABSTRACT On-chip signal routing has become an issue of growing importance in modern VLSI complexity single fux quantum (SFQ) systems. In this paper, diferent routing methods for these systems are de- scribed. The routing methods include either passive transmission lines (PTLs) or Josephson transmission lines (JTLs) as interconnects. Driving multiple SFQ gates is also a challenging issue in automated layout and clock tree synthesis (CTS) due to the limited fanout of SFQ gates. To support multiple fanout, splitters are used to distrib- ute multiple SFQ pulses. These splitters require signifcant area, delay, and power. In this paper, several area and power efcient splitters are proposed for large scale SFQ integrated circuits. A pri- mary issue within a long SFQ interconnect is resonance efects due to the imperfect match between the PTLs and Josephson junctions. A repeater insertion methodology for long interconnect to reduce and manage these resonance efects is also described. Summariz- ing, guidelines and tradeofs appropriate for automated layout and synthesis are described for driving long and short interconnect in VLSI complexity SFQ systems. KEYWORDS Single fux quantum, superconductive integrated circuits, super- conductive digital electronics. ACM Reference Format: Tahereh Jabbari and Eby G. Friedman. 2020. Global Interconnects in VLSI Complexity Single Flux Quantum Systems. In System-Level Interconnect - Problems and Pathfnding Workshop (SLIP ’20), November 5, 2020, San Diego, CA, USA. ACM, New York, NY, USA, 7 pages. https://doi.org/10.1145/3414622. 3431911 1 INTRODUCTION Superconductive single fux quantum (SFQ) technology is one of the most promising beyond-CMOS technologies for ultra-high speed and ultra-low power digital applications [1]. Signifcant develop- ment in the design and manufacture of superconductive electron- ics for prospective exascale computing systems has led to device densities exceeding 600,000 junctions/cm 2 and circuit speeds ap- proaching 770 GHz [2ś5]. Recent progress in the fabrication of Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for proft or commercial advantage and that copies bear this notice and the full citation on the frst page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specifc permission and/or a fee. Request permissions from permissions@acm.org. SLIP ’20, November 5, 2020, San Diego, CA, USA © 2020 Association for Computing Machinery. ACM ISBN 978-1-4503-8106-2/20/11. . . $15.00 https://doi.org/10.1145/3414622.3431911 CMOS JTL PTL Length (um) Energy (J) 10 -19 10 -18 10 -17 10 -16 10 -15 10 -14 10 -13 10 -12 Figure 1: Energy vs. length of CMOS (dash line), JTL (solid line), and PTL with one Josephson junction in the receiver (dash-dotted line) [10ś14]. SFQ circuits emphasizes the need for advanced EDA tools targeting SFQ design and analysis. While certain principles and techniques commonly used in CMOS are applicable to SFQ technology, sev- eral notable diferences between these digital circuit families exist. Novel algorithms, methodologies, and tools are therefore required to enhance the design and analysis of VLSI complexity SFQ circuits and systems. An important characteristic of SFQ circuits is absolute zero DC resistance interconnects [6]. SFQ circuits utilize two distinct types of interconnect - active Josephson transmission lines (JTL) and passive transmission lines (PTL), composed of a microstrip or stripline with a matched driver and receiver [7ś9]. A comparison of the energy dissipated by interconnects for CMOS and SFQ is shown in Fig. 1. The energy of a 16 nm CMOS interconnect technology is evaluated with an RLC model [10]. The energy of a chain of JTLs increases linearly with distance between gates. The PTL line exhibits a constant energy independent of length. The energy of the CMOS interconnect is approximately six orders of magnitude greater than the energy dissipated by a passive superconductive interconnect [11ś14]. The physical design and layout of SFQ circuits play an important role in the timing characteristics of high speed VLSI complexity SFQ systems. The layout of these large scale SFQ circuits requires automated design methodologies. Recent progress in automated layout tools provides efective techniques for clock tree synthe- sis, and placement and routing of VLSI complexity SFQ circuits [15ś17]. Two diferent approaches exist for routing signals in SFQ systems. These routing approaches support either short or long superconductive interconnects. A challenging issue in automated routing methodologies in in- tegrated SFQ circuits is the limited fanout of SFQ gates. Most SFQ