834 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. zyxw 43, NO. zyxw 5, MAY 1996 Improvement of RF Performance of GaAslSi MESFET’s Using Buried Oxygen Implantation S. Sriram, R. L. Messham, T. J. Smith, and G. W. Eldridge zyxwvuts ._ zyxwvu Abstract- A novel buried oxygen implantation (BOI) procedure is described to reduce parasitics and improve RF performance of GaAslSi MESFET’s. Devices fabricated with this procedure show output conduc- tance of less than 8.5 mS/mm which is the lowest reported to date for GaAdSi MESFET’s. These results are particularly important to improve the power performance of GaAs/Si MESFET’s. I. INTRODUCTION GaAs on Si technology is very attractive due to the possibility of monolithic co-integration of GaAs and Si circuit functions and also due to the low cost, large diameter, and high thermal conductivity of Si substrates. Despite significant progress made to date, the high- ‘ frequency performance in this material system is limited by increased device parasitics, mainly a higher output conductance and capacitance in GaAslSi than in similar GaAslGaAs MESFET’s [l], [2]. It is essential to reduce the output parasitics significantly to improve RF performance, and in particular the RF power performance of GaAs/Si MESFET’s. In an earlier work [3] we attributed the higher RF output conductance to capacitive coupling of a thin parasitic conduction layer in GaAs near the GaAs/Si interface. A similar parasitic conduction effect has also been reported in MBE grown GaAs/Si by Chand et zyxwvutsr al. zyxwvutsrqpo [4]. Recently, growth on Si buffer layers [ l ] was introduced in an effort to improve the GaAs on Si interface. The purpose of the present work is to discuss a novel Buried Oxygen Implantation (BOI) scheme to eliminate interfacial conduction and reduce RF parasitics. Devices fabricated with this method show output conductance of less than 8.5 mS/mm which is the lowest obtained to date in any GaAslSi MESFET’s. GaAs/Si device structures in this work were grown on 3-in diame- ter high-resistivity (2.3 KR-cm) float-zone silicon substrates using low-pressure (-70 torr) metal organic chemical vapor deposition (MOCVD). The Buried Oxygen Implanted (BOI) wafers were grown using the following procedure: First, a 0.5-pm thick undoped GaAs buffer layer was deposited on silicon substrates using a standard two-step growth procedure described earlier [3]. Following this the wafers were taken out of the reactor and implanted with 3E14/cm2, I6Of at 385 KV to eliminate the parasitic conduction layer at the GaAs/Si interface. Oxygen implantation was chosen for its known thermal stability [5], [6], and the accelerating voltage was designed to give a peak doping at the interface. After implantation the remaining device structure consisting of an additional 1.5-pm undoped buffer, n-channel (1.5 x iO1?/cm3, 2500 A), and an n+ contact layer were grown in a second deposition step. For comparison, Manuscript received November 16, 1994; revised May 8, 1995. The review of this brief was arranged by Editor zyxwvutsrq J. Xu. This work was supported in part by the Air Force Office of Scientific Research and Rome Laboratory, Hanscom Air Force Base, under Contract #F19628-88-C-0114 and Contract Monitors Dr. P. Carr and Capt. Steinbeck. The authors are with Northrop Grumman Science and Technology Center, (formerly part of Westinghouse Science & Technology Center), Pittsburgh, PA 15235.5098 USA. Publisher Item Identifier S 0018-9383(96)03382-5. * * Source Fig. 1. M E S E T small-signal equivalent circuit model. reference wafers without the oxygen implant were-also grown using the same procedures but with no growth interruption. In independent experiments we verified that growth interruption alone did not reduce the parasitic conduction. After epitaxial regrowth all wafers showed good morphology indicating their suitability for device fabrication. Double recessed MESFET’s with 0.5-pm gates defined by E-beam lithography were fabricated using the procedures described earlier 171. The tested devices had an interdigitated structure with air-bridged source interconnects, and eight gate fingers for a total gate periphery, IVG, of 600 pm. DC characteristics of both BO1 and reference wafers were similar with excellent pinch-off obtained for both cases. S-parameters of these devices were measured on-wafer using a HP 8510B Network analyzer and Cascade Microtech RF wafer prober. Parasitic effects were examined using the conventional FET equivalent circuit model shown in Fig. 1. The output conductance, Gas and the output capacitance, zyxw Cas as shown in Fig. 1, were calculated using the relationships [8], Gas - Re(yZz), and cds - Im(yznSy12) where y12 and yz2 are the y-parameters calculated from the measured S-parameters. It may be noted that these approximate expressions for Gds and cds are basically obtained by neglecting the effect of series inductance and resistances in the model, a condition which is usually valid at frequencies less than 10 GHz for the small periphery MESFET’s such as considered here. Further details of these extraction procedures can be found in [8] and [9]. The calculated Gds and values are shown in Figs. 2 and 3. It can be seen that reference GaAslSi MESFET’s show higher Gds and Cds values and also an anomalous frequency dependence not included in the conventional device models. In contrast, in BO1 devices both Gds and cds are lower and remain nearly independent of frequency similar to that observed in GaAs/GaAs MESFET’s. A comparison with the data compiled in [l] shows that the BO1 devices show the lowest output conductance observed to date in GaAs/Si MESFET’s and is nearly a factor of 2 lower than the best previous result [I]. Our analysis indicates that the lower output conductance is the main reason for the improved the small-signal gain (MAGMSG) at higher frequencies for BO1 devices as shown in Fig. 4 (2.5 dB higher at 20 GHz). The low Gds values are also essential to improve power output, gain, and efficiency of GaAslSi power MESFET’s. These improvements are 0018-9383/96$05.00 zyxwvut 0 1996 IEEE