Architectural Synthesis with Interconnection Cost Control JEGO Christophe, CASSEAU Emmanuel & MARTlN Eric LEST ER Lahoratory, UBS Unh'ersity, France Tel: (+33) 2.97.87.45.65 Fax: (+33) 2.97.87.45.00 E-mail: {First-name.SlmzumellZi;univ-llhs.frhllp:/llesler.zmiv-u bsj;': 8080/ Abstract: Keywords: Architectural synthesis tools map algorithms to architectures under various constraints and quickly providc estimations of area and performance. However. these tools do not take the intcrconnection cost into account whereas it bccomes predominant with the technology dccrease and the application complexity incrcasc. A way to control costly interconnections during the architcctural proccss is prcscnted in this paper. Architcctural synthesis, digital ASIC dcsign, sub-micron tcchnologies, interconncction cost INTRODUCTION Recent advances in VLSI technology lead to new design methodologies like architectural synthesis, so called behavioral synthesis. Architectural synthesis enables a significant productivity increase by raising the abstraction level of digital designs. This process, which explores the space of possible designs, reaches the "best" architectural solution satisfying a set of constraints such as propagation time, area or power dissipation. However, The original version of this chapter was revised: The copyright line was incorrect. This has been corrected. The Erratum to this chapter is available at DOI: © IFIP International Federation for Information Processing 2000 L. M. Silveira et al. (eds.), VLSI: Systems on a Chip 10.1007/978-0-387-35498-9_57